On 8/19/22 16:10, Tanel Poder wrote:
Oh, the world is changing, PCIe (especially PCIe 5.0 and future 6.0) latency and throughput are so good, so that it's getting pretty close to the RAM speed as far as the transport goes. So (now that Intel killed Optane) it's worth keeping an eye on the Compute Express Link (CXL) standard. With CPU support, it's basically like cache coherent system memory, but accessed over PCIe5.0+ links. It's even possible to connect large boards full of DRAM to multiple separate compute nodes, so in theory someone could build a CXL-based shared global buffer cache used by the entire rack of servers concurrently, without needing RAC GC/LMS processes to ship blocks around.
And also DDR5 DRAM is emerging fast. You will also need larger L3 and L2 caches, as well as larger TLB. I am waiting for Oracle to make RDBMS available on arm64 Linux architecture. Unfortunately, I haven't found the description of memory channel architecture on multi-core ARM chips. This is the best I've found:
https://en.wikipedia.org/wiki/Comparison_of_ARM_cores
Of course, RISC chips use more RAM than CISC chips, so whatever
is found to work well for x86_64 processors is unlikely to be
adequate for ARM chips. Does anyone have the information of Oracle
RDBMS on Linux/arm64 architecture?
-- Mladen Gogala Database Consultant Tel: (347) 321-1217 https://dbwhisperer.wordpress.com-- //www.freelists.org/webpage/oracle-l
