[llvm-uc] [PATCH v2 3/3] uc32: Add ISelLowering stub

  • From: Jia Liu <proljc@xxxxxxxxx>
  • To: llvm-uc@xxxxxxxxxxxxx
  • Date: Fri, 30 Nov 2012 15:58:39 +0800

---
 lib/Target/UniCore/UniCoreISelLowering.cpp |  150 ++++++++++++++++++++++++++++
 lib/Target/UniCore/UniCoreISelLowering.h   |   75 ++++++++++++++
 2 files changed, 225 insertions(+)
 create mode 100644 lib/Target/UniCore/UniCoreISelLowering.cpp
 create mode 100644 lib/Target/UniCore/UniCoreISelLowering.h

diff --git a/lib/Target/UniCore/UniCoreISelLowering.cpp 
b/lib/Target/UniCore/UniCoreISelLowering.cpp
new file mode 100644
index 0000000..26788b7
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreISelLowering.cpp
@@ -0,0 +1,150 @@
+//===-- UniCoreISelLowering.cpp - UniCore DAG Lowering Implementation 
-----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that UniCore uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "unicore32-lower"
+#include "UniCore.h"
+#include "UniCoreISelLowering.h"
+#include "UniCoreTargetMachine.h"
+#include "UniCoreTargetObjectFile.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/GlobalVariable.h"
+#include "llvm/Intrinsics.h"
+#include "llvm/CallingConv.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+UniCoreTargetLowering::UniCoreTargetLowering(UniCoreTargetMachine &TM)
+  : TargetLowering(TM, new UniCoreTargetObjectFile()),
+    TM(TM)
+{
+}
+
+SDValue
+UniCoreTargetLowering::LowerOperation(SDValue Op,
+                                      SelectionDAG &DAG) const {
+  switch (Op.getOpcode()) {
+  default:
+    llvm_unreachable("unimplemented operand");
+  }
+}
+
+const char *UniCoreTargetLowering::getTargetNodeName(unsigned Opcode) const {
+  switch (Opcode) {
+  default: return NULL;
+  case UniCoreISD::Ret:           return "UniCoreISD::Ret";
+  }
+}
+
+//===----------------------------------------------------------------------===//
+//                      Calling Convention Implementation
+//===----------------------------------------------------------------------===//
+
+#include "UniCoreGenCallingConv.inc"
+
+SDValue
+UniCoreTargetLowering::LowerCCCArguments(SDValue Chain,
+                                         CallingConv::ID CallConv,
+                                         bool isVarArg,
+                                         const SmallVectorImpl<ISD::InputArg> 
&Ins,
+                                         DebugLoc dl,
+                                         SelectionDAG &DAG,
+                                         SmallVectorImpl<SDValue> &InVals) 
const {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
+
+  // Assign locations to all of the incoming arguments.
+  SmallVector<CCValAssign, 16> ArgLocs;
+  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+                 getTargetMachine(), ArgLocs, *DAG.getContext());
+  CCInfo.AnalyzeFormalArguments(Ins, CC_UniCore);
+
+  assert(!isVarArg && "Varargs not supported yet");
+
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+    CCValAssign &VA = ArgLocs[i];
+
+    unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
+
+    int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
+    SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
+    InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
+                     MachinePointerInfo::getFixedStack(FI),
+                     false, false, false, 0));
+  }
+
+  return Chain;
+}
+
+SDValue
+UniCoreTargetLowering::LowerFormalArguments(SDValue Chain,
+                                            CallingConv::ID CallConv,
+                                            bool isVarArg,
+                                            const 
SmallVectorImpl<ISD::InputArg> &Ins,
+                                            DebugLoc dl,
+                                            SelectionDAG &DAG,
+                                            SmallVectorImpl<SDValue> &InVals) 
const {
+  switch (CallConv) {
+  default:
+    llvm_unreachable("Unsupported calling convention");
+  case CallingConv::C:
+  case CallingConv::Fast:
+    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
+  }
+}
+
+SDValue
+UniCoreTargetLowering::LowerReturn(SDValue Chain,
+                                   CallingConv::ID CallConv, bool isVarArg,
+                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
+                                   const SmallVectorImpl<SDValue> &OutVals,
+                                   DebugLoc dl, SelectionDAG &DAG) const {
+  // CCValAssign - represent the assignment of the return value to a location
+  SmallVector<CCValAssign, 16> RVLocs;
+
+  // CCState - Info about the registers and stack slot.
+  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+                 getTargetMachine(), RVLocs, *DAG.getContext());
+
+  // Analize return values.
+  CCInfo.AnalyzeReturn(Outs, RetCC_UniCore);
+
+  // If this is the first return lowered for this function, add the regs to the
+  // liveout set for the function.
+  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
+    for (unsigned i = 0; i != RVLocs.size(); ++i)
+      if (RVLocs[i].isRegLoc())
+        
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
+  }
+
+  SDValue Flag;
+
+  unsigned Opc = UniCoreISD::Ret;
+  if (Flag.getNode())
+    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
+
+  // Return Void
+  return DAG.getNode(Opc, dl, MVT::Other, Chain);
+}
diff --git a/lib/Target/UniCore/UniCoreISelLowering.h 
b/lib/Target/UniCore/UniCoreISelLowering.h
new file mode 100644
index 0000000..324fdaa
--- /dev/null
+++ b/lib/Target/UniCore/UniCoreISelLowering.h
@@ -0,0 +1,75 @@
+//===-- UniCoreISelLowering.h - UniCore DAG Lowering Interface --*- C++ 
-*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that UniCore uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef UNICOREISELLOWERING_H
+#define UNICOREISELLOWERING_H
+
+#include "UniCore.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetLowering.h"
+
+namespace llvm {
+
+  namespace UniCoreISD {
+    enum {
+      // Start the numbering from where ISD NodeType finishes.
+      FIRST_NUMBER = ISD::BUILTIN_OP_END,
+
+      // Return from subroutine
+      Ret
+    };
+  }
+
+  
//===--------------------------------------------------------------------===//
+  // TargetLowering Implementation
+  
//===--------------------------------------------------------------------===//
+
+  class UniCoreTargetLowering : public TargetLowering  {
+  public:
+    explicit UniCoreTargetLowering(UniCoreTargetMachine &TM);
+
+    /// LowerOperation - Provide custom lowering hooks for some operations.
+    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+
+    /// getTargetNodeName - This method returns the name of a target specific
+    //  DAG node.
+    virtual const char *getTargetNodeName(unsigned Opcode) const;
+
+  private:
+    const UniCoreTargetMachine &TM;
+
+    SDValue LowerCCCArguments(SDValue Chain,
+                              CallingConv::ID CallConv,
+                              bool isVarArg,
+                              const SmallVectorImpl<ISD::InputArg> &Ins,
+                              DebugLoc dl,
+                              SelectionDAG &DAG,
+                              SmallVectorImpl<SDValue> &InVals) const;
+
+    SDValue LowerFormalArguments(SDValue Chain,
+                                 CallingConv::ID CallConv, bool isVarArg,
+                                 const SmallVectorImpl<ISD::InputArg> &Ins,
+                                 DebugLoc dl, SelectionDAG &DAG,
+                                 SmallVectorImpl<SDValue> &InVals) const;
+
+    SDValue LowerReturn(SDValue Chain,
+                        CallingConv::ID CallConv, bool isVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        const SmallVectorImpl<SDValue> &OutVals,
+                        DebugLoc dl, SelectionDAG &DAG) const;
+  };
+}
+
+#endif // UNICOREISELLOWERING_H
-- 
1.7.10.2 (Apple Git-33)


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  • » [llvm-uc] [PATCH v2 3/3] uc32: Add ISelLowering stub - Jia Liu