有两个小问题 1,之前的patch我觉得不应该独立开来 2,typo可以是一个单独的patch 你看下附件两个整理的patch On Thu, Nov 29, 2012 at 5:22 PM, ���f任 (Wei-Ren Chen) <chenwj@xxxxxxxxxxxxxxxxx> wrote: > Add Subtarget, RegisterInfo, and InstrInfo into TargetMahcine. > > Signed-off-by: Chen Wei-Ren <chenwj@xxxxxxxxxxxxxxxxx> > --- > lib/Target/UniCore/UniCoreInstrInfo.cpp | 31 ++++++++++++++++++++ > lib/Target/UniCore/UniCoreInstrInfo.h | 42 > +++++++++++++++++++++++++++ > lib/Target/UniCore/UniCoreRegisterInfo.cpp | 13 ++++++++ > lib/Target/UniCore/UniCoreRegisterInfo.h | 9 ++++++ > lib/Target/UniCore/UniCoreTargetMachine.cpp | 11 ++++-- > lib/Target/UniCore/UniCoreTargetMachine.h | 22 +++++++++++--- > 6 files changed, 119 insertions(+), 9 deletions(-) > create mode 100644 lib/Target/UniCore/UniCoreInstrInfo.cpp > create mode 100644 lib/Target/UniCore/UniCoreInstrInfo.h > > diff --git a/lib/Target/UniCore/UniCoreInstrInfo.cpp > b/lib/Target/UniCore/UniCoreInstrInfo.cpp > new file mode 100644 > index 0000000..2d044dd > --- /dev/null > +++ b/lib/Target/UniCore/UniCoreInstrInfo.cpp > @@ -0,0 +1,31 @@ > +//===-- UniCoreInstrInfo.cpp - UniCore Instruction Information > -----------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file contains the UniCore implementation of the TargetInstrInfo > class. > +// > +//===----------------------------------------------------------------------===// > + > +#include "UniCoreInstrInfo.h" > +#include "UniCore.h" > +#include "UniCoreTargetMachine.h" > +#include "llvm/Function.h" > +#include "llvm/CodeGen/MachineFrameInfo.h" > +#include "llvm/CodeGen/MachineInstrBuilder.h" > +#include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/Support/ErrorHandling.h" > +#include "llvm/Support/TargetRegistry.h" > + > +#define GET_INSTRINFO_CTOR > +#include "UniCoreGenInstrInfo.inc" > + > +using namespace llvm; > + > +UniCoreInstrInfo::UniCoreInstrInfo(UniCoreTargetMachine &tm) > + : UniCoreGenInstrInfo(), > + RI(tm, *this), TM(tm) {} > diff --git a/lib/Target/UniCore/UniCoreInstrInfo.h > b/lib/Target/UniCore/UniCoreInstrInfo.h > new file mode 100644 > index 0000000..be0d6aa > --- /dev/null > +++ b/lib/Target/UniCore/UniCoreInstrInfo.h > @@ -0,0 +1,42 @@ > +//==-- UniCoreInstrInfo.h - UniCore Instruction Information ---*- C++ > -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file contains the UniCore implementation of the TargetInstrInfo > class. > +// > +//===----------------------------------------------------------------------===// > + > +#ifndef LLVM_TARGET_UNICOREINSTRINFO_H > +#define LLVM_TARGET_UNICOREINSTRINFO_H > + > +#include "UniCoreRegisterInfo.h" > +#include "llvm/Target/TargetInstrInfo.h" > + > +#define GET_INSTRINFO_HEADER > +#include "UniCoreGenInstrInfo.inc" > + > +namespace llvm { > + > +class UniCoreTargetMachine; > + > +class UniCoreInstrInfo : public UniCoreGenInstrInfo { > + const UniCoreRegisterInfo RI; > + UniCoreTargetMachine &TM; > +public: > + explicit UniCoreInstrInfo(UniCoreTargetMachine &TM); > + > + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As > + /// such, whenever a client has an instance of instruction info, it should > + /// always be able to get register info as well (through this method). > + /// > + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } > +}; > + > +} > + > +#endif > diff --git a/lib/Target/UniCore/UniCoreRegisterInfo.cpp > b/lib/Target/UniCore/UniCoreRegisterInfo.cpp > index 08cdbdd..a246a3d 100644 > --- a/lib/Target/UniCore/UniCoreRegisterInfo.cpp > +++ b/lib/Target/UniCore/UniCoreRegisterInfo.cpp > @@ -35,3 +35,16 @@ > UniCoreRegisterInfo::UniCoreRegisterInfo(UniCoreTargetMachine &tm, > const TargetInstrInfo &tii) > : UniCoreGenRegisterInfo(UniCore::PC), TM(tm), TII(tii) { > } > + > +const uint16_t * > +UniCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {} > + > +BitVector > +UniCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {} > + > +void > +UniCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, > + int SPAdj, RegScavenger *RS) const > {} > + > +unsigned > +UniCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {} > diff --git a/lib/Target/UniCore/UniCoreRegisterInfo.h > b/lib/Target/UniCore/UniCoreRegisterInfo.h > index 29c17e4..2a54507 100644 > --- a/lib/Target/UniCore/UniCoreRegisterInfo.h > +++ b/lib/Target/UniCore/UniCoreRegisterInfo.h > @@ -30,6 +30,15 @@ private: > const TargetInstrInfo &TII; > public: > UniCoreRegisterInfo(UniCoreTargetMachine &tm, const TargetInstrInfo &tii); > + > + const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; > + > + BitVector getReservedRegs(const MachineFunction &MF) const; > + > + void eliminateFrameIndex(MachineBasicBlock::iterator II, > + int SPAdj, RegScavenger *RS = NULL) const; > + > + unsigned getFrameRegister(const MachineFunction &MF) const; > }; > > } // end namespace llvm > diff --git a/lib/Target/UniCore/UniCoreTargetMachine.cpp > b/lib/Target/UniCore/UniCoreTargetMachine.cpp > index beaf5d9..1fe51e3 100644 > --- a/lib/Target/UniCore/UniCoreTargetMachine.cpp > +++ b/lib/Target/UniCore/UniCoreTargetMachine.cpp > @@ -23,9 +23,12 @@ extern "C" void LLVMInitializeUniCoreTarget() { > > UniCoreTargetMachine:: > UniCoreTargetMachine(const Target &T, StringRef TT, > - StringRef CPU, StringRef FS, const TargetOptions > &Options, > - Reloc::Model RM, CodeModel::Model CM, > - CodeGenOpt::Level OL) > - : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) > + StringRef CPU, StringRef FS, const TargetOptions > &Options, > + Reloc::Model RM, CodeModel::Model CM, > + CodeGenOpt::Level OL) > + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), > + Subtarget(TT, CPU, FS), > + DL("e-p:32:32:32-i8:8:8-i16:16:16-i32:32:32-n32"), > + InstrInfo(*this) > { > } > diff --git a/lib/Target/UniCore/UniCoreTargetMachine.h > b/lib/Target/UniCore/UniCoreTargetMachine.h > index 12d6bbc..e37f0c5 100644 > --- a/lib/Target/UniCore/UniCoreTargetMachine.h > +++ b/lib/Target/UniCore/UniCoreTargetMachine.h > @@ -15,6 +15,8 @@ > #define UNICORE_TARGETMACHINE_H > > #include "UniCoreRegisterInfo.h" > +#include "UniCoreSubtarget.h" > +#include "UniCoreInstrInfo.h" > #include "llvm/DataLayout.h" > #include "llvm/Target/TargetMachine.h" > > @@ -22,16 +24,26 @@ namespace llvm { > class formatted_raw_ostream; > > class UniCoreTargetMachine : public LLVMTargetMachine { > + UniCoreSubtarget Subtarget; > const DataLayout DL; // Calculates type size & alignment > + UniCoreInstrInfo InstrInfo; > > public: > UniCoreTargetMachine(const Target &T, StringRef TT, > - StringRef CPU, StringRef FS, > - const TargetOptions &Options, > - Reloc::Model RM, CodeModel::Model CM, > - CodeGenOpt::Level OL); > + StringRef CPU, StringRef FS, > + const TargetOptions &Options, > + Reloc::Model RM, CodeModel::Model CM, > + CodeGenOpt::Level OL); > > - virtual const DataLayout *getDataLayout() const { return &DL;} > + virtual const UniCoreSubtarget *getSubtargetImpl() const { return > &Subtarget; } > + > + virtual const DataLayout *getDataLayout() const { return &DL; } > + > + virtual const UniCoreInstrInfo *getInstrInfo() const { return > &InstrInfo; } > + > + virtual const TargetRegisterInfo *getRegisterInfo() const { > + return &InstrInfo.getRegisterInfo(); > + } > }; > } // End llvm namespace > > -- > 1.7.3.4 >
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0001-uc32-style-fix.patch
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0002-uc32-Add-Subtarget-RegisterInfo-and-InstrInfo-into-T.patch
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