[linux-cirrus] Re: EP9312 internal ROM
- From: Eric BENARD / Free <ebenard@xxxxxxx>
- To: linux-cirrus@xxxxxxxxxxxxx
- Date: Sun, 08 May 2005 19:36:53 +0200
David Collier wrote:
> thanks you... now all I need to do is work out how to read ARM assembler
> :-)
>
you will find attached a start of explanation (quick and dirty, sorry).
I didn't dig futher in the serial loader functions & in the function
which are looking for CRUS on SPI & flash CS as I just wanted to see
which registers the bootrom was changing.
Eric
-- Attached file included as plaintext by Ecartis --
-- File: ep9312_bootloader.txt
0x80090000: mov r3, #-2147483648 ; 0x80000000
0x80090004: mov r4, #589824 ; 0x90000
0x80090008: orr r3, r3, r4
0x8009000c: orr r3, r3, #24 ; 0x18
0x80090010: nop (mov r0,r0)
0x80090014: mov pc, r3
=> pc < 80090018
0x80090018: nop (mov r0,r0)
0x8009001c: ldr r0, [pc, #176] ; 0x800900d4
0x80090020: mov r1, #2 ; 0x2
0x80090024: str r1, [r0]
=> 0x80840020 (PEDR) = 0x02 => LED
0x80090028: ldr r0, [pc, #152] ; 0x800900c8
0x8009002c: ldr r1, [pc, #152] ; 0x800900cc
0x80090030: str r1, [r0]
=> 0x80940000 (Watchdog timer Register) = 0xaa55
0x80090034: bl 0x80090984
0x80090038: nop (mov r0,r0)
0x8009003c: bl 0x800909dc
=> Initialize SMC
0x80090040: bl 0x80090828
=> Initialize SDRAM
0x80090044: mov r2, #0 ; 0x0
0x80090048: mov r0, #-2147483648 ; 0x80000000
0x8009004c: mov r1, #9633792 ; 0x930000
0x80090050: orr r0, r0, r1
r0 < 0x80930000
0x80090054: str r2, [r0, #88]
0x80930058 < 0x00 => BootMode Clear Register.
0x80090058: ldr r0, [pc, #116] ; 0x800900d4
r0 < 0x80840020
0x8009005c: mov r1, #1 ; 0x1
0x80090060: str r1, [r0]
0x80840020 < 0x1 => PEDR = 0x1 => LED
0x80090064: ldr r0, [pc, #100] ; 0x800900d0
r0 < 0x8093009c
0x80090068: ldr r1, [r0]
r1 < SysCFG
0x8009006c: tst r1, #256 ; 0x100
0x80090070: bne 0x80090214
if SERIAL BOOT => goto 0x80090214
else (if NORMAL BOOT)
0x80090074: bl 0x80090a4c
0x80090078: bl 0x800900e8
0x8009007c: bl 0x80090168
0x80090080: nop (mov r0,r0)
0x80090084: ldr r0, [pc, #72] ; 0x800900d4
0x80090088: mov r1, #2 ; 0x2
0x8009008c: str r1, [r0]
0x80090090: mov r3, #8192 ; 0x2000
0x80090094: nop (mov r0,r0)
0x80090098: nop (mov r0,r0)
0x8009009c: nop (mov r0,r0)
0x800900a0: nop (mov r0,r0)
0x800900a4: nop (mov r0,r0)
0x800900a8: ldr r0, [pc, #36] ; 0x800900d4
0x800900ac: ldr r1, [r0]
0x800900b0: eor r1, r1, #2 ; 0x2
0x800900b4: str r1, [r0]
0x800900b8: subs r3, r3, #1 ; 0x1
0x800900bc: bne 0x800900b8
0x800900c0: b 0x80090090
0x800900c4: andhi r4, r1, r0
0x800900c8: addhis r0, r4, r0
0x800900cc: andeq r10, r0, r5, asr r10
0x800900d0: umullhis r0, r3, r12, r0
0x800900d4: addhi r0, r4, r0, lsr #32
0x800900d8: addhi r0, r4, r0
0x800900dc: andeq r5, r0, r0, asr #27
0x800900e0: andeq r2, r0, r0, ror #29
0x800900e4: andeq r1, r0, r0, ror r7
*** Normal boot 2
0x800900e8: ldr r0, [pc, #88] ; 0x80090148
0x800900ec: ldr r1, [pc, #2956] ; 0x80090c80
0x800900f0: ldr r2, [pc, #2956] ; 0x80090c84
0x800900f4: ldr r3, [pc, #72] ; 0x80090144
r0 < 0x7
r1 < CRUS
r2 < SURC
r3 < 0x8009014c
0x800900f8: ldr r4, [r3], #4
0x800900fc: ldr r5, [r4]
0x80090100: cmp r1, r5
0x80090104: beq 0x80090134
0x80090108: cmp r2, r5
0x8009010c: beq 0x80090138
0x80090110: add r4, r4, #4096 ; 0x1000
0x80090114: ldr r5, [r4]
0x80090118: cmp r1, r5
0x8009011c: beq 0x8009013c
0x80090120: cmp r2, r5
0x80090124: beq 0x80090140
0x80090128: subs r0, r0, #1 ; 0x1
0x8009012c: bne 0x800900f8
0x80090130: mov pc, lr
0x80090134: add pc, r4, #4 ; 0x4
0x80090138: add pc, r4, #4 ; 0x4
0x8009013c: sub pc, r4, #4096 ; 0x1000
0x80090140: sub pc, r4, #4096 ; 0x1000
0x80090144: andhi r0, r9, r12, asr #2
0x80090148: andeq r0, r0, r7
0x8009014c: andne r0, r0, r0
0x80090150: andcs r0, r0, r0
0x80090154: andcc r0, r0, r0
0x80090158: andvs r0, r0, r0
0x8009015c: andvc r0, r0, r0
0x80090160: andgt r0, r0, r0
0x80090164: andnv r0, r0, r0
0x80090168: ldr r0, [pc, #80] ; 0x800901c0
0x8009016c: ldr r3, [pc, #68] ; 0x800901b8
0x80090170: ldr r5, [pc, #64] ; 0x800901b8
r0 < 0x1a2b3c4d
r3 < 0
r5 < 0
0x80090174: str r0, [r3]
0x80090178: ldr r2, [r3]
0x8009017c: cmp r0, r2
0x80090180: beq 0x8009018c
0x80090184: ldr r3, [pc, #48] ; 0x800901bc
0x80090188: ldr r5, [pc, #44] ; 0x800901bc
0x8009018c: ldr r0, [pc, #28] ; 0x800901b0
0x80090190: ldr r1, [pc, #28] ; 0x800901b4
r3 < 0x80014000
r5 < 0x80014000
r0 < 0x800901c4
r1 < 0x80090210
0x80090194: sub r2, r1, r0
0x80090198: mov r2, r2, lsr #2
0x8009019c: ldr r4, [r0], #4
0x800901a0: str r4, [r3], #4
0x800901a4: subs r2, r2, #1 ; 0x1
0x800901a8: bne 0x8009019c
0x800901ac: mov pc, r5
0x800901b0: andhi r0, r9, r4, asr #3
0x800901b4: andhi r0, r9, r0, lsl r2
0x800901b8: andeq r0, r0, r0
0x800901bc: andhi r4, r1, r0
0x800901c0: bne 0x80b5f2fc
0x800901c4: b 0x800901e8
0x800901c8: b 0x800901e8
0x800901cc: b 0x800901cc
0x800901d0: b 0x800901d0
0x800901d4: b 0x800901d4
0x800901d8: b 0x800901d8
0x800901dc: b 0x800901dc
0x800901e0: b 0x800901e0
0x800901e4: nop (mov r0,r0)
0x800901e8: mov r0, #-2147483648 ; 0x80000000
0x800901ec: mov r1, #8650752 ; 0x840000
0x800901f0: orr r0, r0, r1
r0 < 0x80840000
0x800901f4: mov r1, #1 ; 0x1
0x800901f8: mov r2, #65536 ; 0x10000
0x800901fc: str r1, [r0, #32]
0x80840020 < 0x1 PEDR => LED
0x80090200: subs r2, r2, #1 ; 0x1
0x80090204: bne 0x80090200
0x80090208: eor r1, r1, #1 ; 0x1
0x8009020c: b 0x800901f8
==> blink green led if all boot options failed.
0x80090210: andeq r0, r0, r0
*** start of SERIAL BOOT
0x80090214: ldr r12, [pc, #352] ; 0x8009037c
r12 < 0x808c0000
0x80090218: mov r1, #0 ; 0x0
0x8009021c: str r1, [r12, #4]
0x808c0004 < 0x00 =>
0x80090220: str r1, [r12, #12]
0x80090224: mov r1, #46 ; 0x2e
0x80090228: str r1, [r12, #16]
0x8009022c: mov r1, #96 ; 0x60
0x80090230: str r1, [r12, #8]
0x80090234: mov r1, #3 ; 0x3
0x80090238: str r1, [r12, #256]
0x8009023c: mov r1, #1 ; 0x1
0x80090240: str r1, [r12, #20]
0x80090244: mov r0, #60 ; 0x3c
0x80090248: strb r0, [r12]
0x8009024c: mov r3, #2048 ; 0x800
0x80090250: ldr r2, [pc, #-404] ; 0x800900c4
r2 < 0x80140000 (MACFIFO SRAM)
0x80090254: ldr r11, [pc, #-392] ; 0x800900d4
r11 < 0x80840020 (PEDR) => LED
0x80090258: mov r10, #1 ; 0x1
0x8009025c: str r10, [r11]
0x80090260: mov r5, #0 ; 0x0
0x80090264: mov r4, #0 ; 0x0
0x80090268: mov r9, #8 ; 0x8
0x8009026c: ldr r1, [r12, #24]
0x80090270: tst r1, #16 ; 0x10
0x80090274: bne 0x8009026c
0x80090278: ldrb r0, [r12]
0x8009027c: and r6, r5, #3 ; 0x3
0x80090280: mul r7, r6, r9
0x80090284: mov r8, r0, lsl r7
0x80090288: orr r4, r4, r8
0x8009028c: add r5, r5, #1 ; 0x1
0x80090290: ldr r1, [r12, #24]
0x80090294: tst r1, #16 ; 0x10
0x80090298: bne 0x80090290
0x8009029c: ldrb r0, [r12]
0x800902a0: and r6, r5, #3 ; 0x3
0x800902a4: mul r7, r6, r9
0x800902a8: mov r8, r0, lsl r7
0x800902ac: orr r4, r4, r8
0x800902b0: cmp r6, #3 ; 0x3
0x800902b4: add r5, r5, #1 ; 0x1
0x800902b8: bne 0x80090290
0x800902bc: str r4, [r2], #4
0x800902c0: ldr r10, [r11]
0x800902c4: eor r10, r10, #1 ; 0x1
0x800902c8: str r10, [r11]
0x800902cc: cmp r3, #2048 ; 0x800
0x800902d0: beq 0x800902ec
0x800902d4: mov r4, #0 ; 0x0
0x800902d8: subs r3, r3, #4 ; 0x4
0x800902dc: bne 0x80090290
0x800902e0: mov r0, #62 ; 0x3e
0x800902e4: strb r0, [r12]
0x800902e8: ldr pc, [pc, #-556] ; 0x800900c4
pc < 0x80014000 (MACFIFO SRAM)
0x800902ec: ldr r0, [pc, #140] ; 0x80090380
r0 < UART
0x800902f0: cmp r0, r4
0x800902f4: beq 0x80090308
0x800902f8: ldr r0, [pc, #132] ; 0x80090384
r0< UANT
0x800902fc: cmp r0, r4
0x80090300: beq 0x8009032c
0x80090304: b 0x800902d4
0x80090308: mov r0, #0 ; 0x0
0x8009030c: ldr r1, [r12, #24]
0x80090310: tst r1, #128 ; 0x80
0x80090314: beq 0x8009030c
0x80090318: strb r0, [r12]
0x8009031c: add r0, r0, #1 ; 0x1
0x80090320: cmp r0, #256 ; 0x100
0x80090324: beq 0x80090308
0x80090328: b 0x8009030c
0x8009032c: ldr r3, [pc, #52] ; 0x80090368
0x80090330: ldr r4, [pc, #52] ; 0x8009036c
0x80090334: sub r4, r4, r3
0x80090338: ldr r1, [r12, #24]
0x8009033c: tst r1, #128 ; 0x80
0x80090340: beq 0x80090338
0x80090344: ldrb r5, [r3], #1
0x80090348: strb r5, [r12]
0x8009034c: subs r4, r4, #1 ; 0x1
0x80090350: bne 0x80090338
0x80090354: mov r4, #65536 ; 0x10000
0x80090358: subs r4, r4, #1 ; 0x1
0x8009035c: bne 0x80090358
0x80090360: b 0x8009032c
0x80090364: b 0x80090364
0x80090820: beq 0x8089bca8
0x80090824: andeq r0, sp, sp, lsl #20
** start of SDRAM Initialization
0x80090828: ldr r1, [pc, #232] ; 0x80090918
r1 < 0x00000bb8
0x8009082c: subs r1, r1, #1 ; 0x1
0x80090830: bne 0x8009082c
loop 0xbb8 times
0x80090834: ldr r0, [pc, #-1900] ; 0x800900d0
r0 < 0x8093009c
0x80090838: ldr r1, [r0]
r1 < SyscFG
0x8009083c: and r2, r1, #192 ; 0xc0
0x80090840: cmp r2, #192 ; 0xc0
0x80090844: beq 0x80090860
0x80090848: cmp r2, #128 ; 0x80
0x8009084c: beq 0x80090860
32 bits => goto 0x80090860
0x80090850: ldr r5, [pc, #256] ; 0x80090958
0x80090854: ldr r8, [pc, #228] ; 0x80090940
0x80090858: str r5, [r8]
0x8009085c: b 0x8009086c
16 bits :
0x80060010 < 0x002a002c => SDRAMCfg0
goto 0x8009086c
0x80090860: ldr r5, [pc, #244] ; 0x8009095c
0x80090864: ldr r8, [pc, #212] ; 0x80090940
0x80090868: str r5, [r8]
32 bits :
0x80060010 < 0x002a0028 => SDRAMCfg0
0x8009086c: ldr r5, [pc, #220] ; 0x80090950
0x80090870: ldr r8, [pc, #212] ; 0x8009094c
0x80090874: str r5, [r8]
0x8006001c < 0x01220028 => SDRAMCfg3
0x80090878: ldr r1, [pc, #152] ; 0x80090918
0x8009087c: subs r1, r1, #1 ; 0x1
0x80090880: bne 0x8009087c
loop 0xbb8 times
0x80090884: ldr r8, [pc, #148] ; 0x80090920
0x80090888: ldr r5, [pc, #160] ; 0x80090930
0x8009088c: str r5, [r8]
0x80060004 < 0x80000003 => INIT
0x80090890: ldr r1, [pc, #132] ; 0x8009091c
0x80090894: subs r1, r1, #1 ; 0x1
0x80090898: bne 0x80090894
loop 0x1770 times
0x8009089c: ldr r8, [pc, #124] ; 0x80090920
0x800908a0: ldr r5, [pc, #128] ; 0x80090928
0x800908a4: str r5, [r8]
0x80060004 < 0x80000001 => Precharge ALL
0x800908a8: ldr r8, [pc, #132] ; 0x80090934
0x800908ac: mov r5, #10 ; 0xa
0x800908b0: str r5, [r8]
0x80060008 < 0xa => Refresh Cycles = 10
0x800908b4: ldr r1, [pc, #92] ; 0x80090918
0x800908b8: subs r1, r1, #1 ; 0x1
0x800908bc: bne 0x800908b8
loop 0xbb8 times
0x800908c0: ldr r8, [pc, #108] ; 0x80090934
0x800908c4: ldr r5, [pc, #108] ; 0x80090938
0x800908c8: str r5, [r8]
0x80060008 < 0x204 => Refresh Cucles = 0x204
0x800908cc: cmp r2, #192 ; 0xc0
0x800908d0: beq 0x800908e4
0x800908d4: cmp r2, #128 ; 0x80
0x800908d8: beq 0x800908e4
32 bits => goto 0x800908e4
0x800908dc: ldr r6, [pc, #140] ; 0x80090970
0x800908e0: b 0x800908e8
16 bits => r6 < 0xc0046600
goto 0x800908e8
0x800908e4: ldr r6, [pc, #136] ; 0x80090974
32 bits => r6 < 0xc008c800
0x800908e8: ldr r7, [pc, #144] ; 0x80090980
r7 < 0xf000c800
0x800908ec: ldr r8, [pc, #44] ; 0x80090920
r8 < 0x80060004
0x800908f0: ldr r5, [pc, #52] ; 0x8009092c
r5 < 0x80000002
0x800908f4: str r5, [r8]
0x80060004 < 0x80000002 => MRS Mode
0x800908f8: ldr r5, [r6]
read @ 0xc008c800 if 32 bits or 0xc0046600 if 16 bits
0x800908fc: ldr r5, [r7]
read @ 0xf000c800
0x80090900: ldr r8, [pc, #24] ; 0x80090920
r8 < 0x80060004
0x80090904: ldr r5, [pc, #24] ; 0x80090924
r5 < 0x80000000
0x80090908: str r5, [r8]
==> out of MRS mode
0x8009090c: mov pc, lr
go back to caller
0x80090910: andhi r0, r0, r0, lsl #24
0x80090914: andeq r0, r0, r1
0x80090918: streqh r0, [r0], -r8
0x8009091c: andeq r1, r0, r0, ror r7
0x80090920: andhi r0, r6, r4
0x80090924: andhi r0, r0, r0
0x80090928: andhi r0, r0, r1
0x8009092c: andhi r0, r0, r2
0x80090930: andhi r0, r0, r3
0x80090934: andhi r0, r6, r8
0x80090938: andeq r0, r0, r4, lsl #4
0x8009093c: andhi r0, r6, r12
0x80090940: andhi r0, r6, r0, lsl r0
0x80090944: andhi r0, r6, r4, lsl r0
0x80090948: andhi r0, r6, r8, lsl r0
0x8009094c: andhi r0, r6, r12, lsl r0
0x80090950: teqeq r2, r8, lsr #32
0x80090954: teqeq r2, r8
0x80090958: eoreq r0, r10, r12, lsr #32
0x8009095c: eoreq r0, r10, r8, lsr #32
0x80090960: teqeq r2, r12
0x80090964: teqeq r2, r8
0x80090968: andgt r6, r0, r0, lsl #12
0x8009096c: andgt r12, r0, r0, lsl #16
0x80090970: andgt r6, r4, r0, lsl #12
0x80090974: andgt r12, r8, r0, lsl #16
0x80090978: andle r12, r0, r0, lsl #16
0x8009097c: andnv r12, r8, r0, lsl #16
0x80090980: andnv r12, r0, r0, lsl #16
*** start of CPU initialization
0x80090984: mov r12, lr
=> backup caller address into R12 for return
0x80090988: ldr r0, [pc, #768] ; 0x80090c90
0x8009098c: mov r1, #170 ; 0xaa
0x80090990: str r1, [r0, #192]
=> 0x809300C0 < 0xAA => unlock syscon regs
0x80090994: mov r1, #262144 ; 0x40000
0x80090998: str r1, [r0, #128]
=> 0x80930080 < 0x40000 => device cfg => UART1 Enable
0x8009099c: mov r0, #120 ; 0x78
0x800909a0: mcr 15, 0, r0, cr1, cr0, {0}
=> ARM920T control register < 0x78 :
31:30 : 00 => Fast bus mode
14 : 0 => Random replacement
13 : 0 => exception @ 0
12 : 0 => ICache disabled
9 : 0 => R bit
8 : 0 => S bit
7 : 0 => little endian
6:3 : 1 => reserved
2 : 0 => DCache disabled
1 : 0 => fault checking disabled
0 : 0 => MMU disabled
0x800909a4: nop (mov r0,r0)
0x800909a8: nop (mov r0,r0)
0x800909ac: nop (mov r0,r0)
0x800909b0: nop (mov r0,r0)
0x800909b4: nop (mov r0,r0)
0x800909b8: mov pc, r12
=> go back to caller
0x800909bc: ldr r4, [pc, #12] ; 0x800909d0
0x800909c0: subs r4, r4, #1 ; 0x1
0x800909c4: bne 0x800909c0
0x800909c8: mov pc, lr
0x800909cc: andeq r0, r0, r0
0x800909d0: andeq r0, r0, r0, lsl #5
0x800909d4: andeq r9, r3, r7, ror #17
0x800909d8: andeq r11, r3, r8, lsl r11
*** start of SMC Controler initialization
0x800909dc: ldr r0, [pc, #92] ; 0x80090a40
r0 < 0x80080000
0x800909e0: ldr r1, [pc, #92] ; 0x80090a44
r1 < 0x00001c61
0x800909e4: ldr r2, [pc, #-2332] ; 0x800900d0
r2 < 0x8093009c
0x800909e8: ldr r3, [r2]
r3 < syscfg
0x800909ec: and r4, r3, #192 ; 0xc0
0x800909f0: cmp r4, #192 ; 0xc0
syscfg & 0xc0 == 0xc0 => b 0x80090a18 (32 bits)
0x800909f4: beq 0x80090a18
0x800909f8: cmp r4, #128 ; 0x80
syscfg & 0xc0 == 0x80 => b 0x80090a18 (32 bits)
0x800909fc: beq 0x80090a18
0x80090a00: cmp r4, #64 ; 0x40
syscfg & 0xc0 == 0x40 => b 0x80090a20 (16 bits)
0x80090a04: beq 0x80090a20
0x80090a08: ldr r1, [pc, #56] ; 0x80090a48
r1 < 0x00001861
0x80090a0c: cmp r4, #0 ; 0x0
syscfg & 0xc0 == 0x00 => b 0x80090a24 (8 bits if ASDO 0 / 16 bits if ASDO 1)
0x80090a10: beq 0x80090a24
0x80090a14: b 0x80090a24
32 bits => r1 < 0x20001c61
0x80090a18: orr r1, r1, #536870912 ; 0x20000000
0x80090a1c: b 0x80090a24
16 bits => r1 < 0x10001c61
0x80090a20: orr r1, r1, #268435456 ; 0x10000000
0x80090a24: str r1, [r0]
0x80090a28: str r1, [r0, #4]
0x80090a2c: str r1, [r0, #8]
0x80090a30: str r1, [r0, #12]
0x80090a34: str r1, [r0, #24]
0x80090a38: str r1, [r0, #28]
initialize SMCBCRx
32 bits => 0x80080000 < 0x20001c61
16 bits => 0x80080000 < 0x10001c61
16 bits & ASDO 1 => 0x80080000 < 0x00001861
8 bits & ADSO 0 => 0x80080000 < 0x00001861
0x80090a3c: mov pc, lr
go back to caller
0x80090a40: andhi r0, r8, r0
0x80090a44: andeq r1, r0, r1, ror #24
0x80090a48: andeq r1, r0, r1, ror #16
*** start of NORMAL BOOT
0x80090a4c: mov r9, lr
backup caller adress
0x80090a50: bl 0x80090ac0
goto > 0x80090ac0 =< SPI
0x80090a54: bl 0x80090a60
goto > 0x80090a60
0x80090a58: mov lr, r9
0x80090a5c: mov pc, lr
! SPI :
0x80090a60: stmdb sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, lr}
0x80090a64: mov r12, lr
0x80090a68: mov r1, #1 ; 0x1
0x80090a6c: ldr r2, [pc, #540] ; 0x80090c90
r2 < 0x80930000
0x80090a70: ldr r3, [r2, #68]
r3 < 0w80930044 ScratchREG 1
0x80090a74: and r3, r3, r1
0x80090a78: cmp r3, r1
0x80090a7c: beq 0x80090ab0
if 0x1 > goto 0x80090ab0
0x80090a80: mov r3, #2048 ; 0x800
0x80090a84: mov r4, #4 ; 0x4
0x80090a88: ldr r5, [pc, #556] ; 0x80090cbc
r5 < 0x80140000
0x80090a8c: bl 0x80090b04
goto > 0x80090b04
0x80090a90: ldmeqia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, pc}
0x80090a94: mov r0, r4
0x80090a98: bl 0x80090c28
0x80090a9c: str r0, [r5], #4
0x80090aa0: subs r3, r3, #4 ; 0x4
0x80090aa4: add r4, r4, #4 ; 0x4
0x80090aa8: bne 0x80090a94
0x80090aac: ldr pc, [pc, #524] ; 0x80090cc0
pc < 0x80014000 (MACFIFO SRAM)
0x80090ab0: mov r1, #1 ; 0x1
0x80090ab4: ldr r2, [pc, #468] ; 0x80090c90
r2 < 0x80930000
0x80090ab8: str r1, [r2, #68]
0x80930044 < r1 (ScratchREG 1)
0x80090abc: mov pc, r12
Normal Boot 1 => SPI Init
0x80090ac0: ldr r11, [pc, #468] ; 0x80090c9c
0x80090ac4: ldr r10, [pc, #432] ; 0x80090c7c
r11 < 0x808a0000
r10 < 0x80090cd4
0x80090ac8: mov r1, #4 ; 0x4
0x80090acc: str r1, [r11, #16]
0x808a0010 < 0x04 => SPI Clock Prescale Register
0x80090ad0: ldr r1, [pc, #456] ; 0x80090ca0
r1 < 0x000001c7
0x80090ad4: str r1, [r11]
0x808a0000 < 0x1c7 => SPICR0
0x80090ad8: mov r1, #16 ; 0x10
0x80090adc: str r1, [r11, #4]
0x808a0004 < 0x10 => SPICR1
0x80090ae0: ldr sp, [pc, #464] ; 0x80090cb8
sp < 0x800148fc
0x80090ae4: mov r0, #0 ; 0x0
0x80090ae8: mov r1, #63 ; 0x3f
0x80090aec: str r0, [sp]
0x800148fc < 0 => MACFIFO SDRAM < 0
0x80090af0: sub sp, sp, #4 ; 0x4
0x80090af4: subs r1, r1, #1 ; 0x1
0x80090af8: bne 0x80090aec
0x80090afc: ldr sp, [pc, #436] ; 0x80090cb8
sp < 0x800148fc
0x80090b00: mov pc, lr
*** start of boot
0x80090b04: stmdb sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, lr}
0x80090b08: mov r1, #3 ; 0x3
0x80090b0c: mov r0, #0 ; 0x0
0x80090b10: ldr r2, [pc, #360] ; 0x80090c80
r2 < CRUS
0x80090b14: bl 0x80090c28
0x80090b18: cmp r0, r2
0x80090b1c: beq 0x80090b30
0x80090b20: ldr r2, [pc, #348] ; 0x80090c84
r2 < SURC
0x80090b24: cmp r0, r2
0x80090b28: beq 0x80090b38
0x80090b2c: b 0x80090b40
0x80090b30: cmp r1, #0 ; 0x0
0x80090b34: ldmia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, pc}
0x80090b38: cmp r1, #0 ; 0x0
0x80090b3c: ldmia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, pc}
0x80090b40: subs r1, r1, #1 ; 0x1
0x80090b44: bne 0x80090b0c
0x80090b48: ldmia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, r10, pc}
*** start of ?
0x80090b4c: stmdb sp!, {r2, r3, r4, r5, r6, r7, r8, r9, lr}
0x80090b50: mov r4, r1
0x80090b54: and r1, r0, #255 ; 0xff
0x80090b58: mov r2, r0, lsr #8
0x80090b5c: and r2, r2, #255 ; 0xff
0x80090b60: mov r3, r0, lsr #16
0x80090b64: and r3, r3, #255 ; 0xff
0x80090b68: mov r5, #3 ; 0x3
0x80090b6c: mov r6, #0 ; 0x0
0x80090b70: cmp r4, #1 ; 0x1
0x80090b74: beq 0x80090b88
0x80090b78: cmp r4, #2 ; 0x2
0x80090b7c: beq 0x80090bac
0x80090b80: cmp r4, #3 ; 0x3
0x80090b84: beq 0x80090bc0
0x80090b88: tst r0, #256 ; 0x100
0x80090b8c: bne 0x80090b98
0x80090b90: mov r5, #3 ; 0x3
0x80090b94: b 0x80090b9c
0x80090b98: mov r5, #11 ; 0xb
0x80090b9c: strh r5, [r11, #8]
0x80090ba0: strh r1, [r11, #8]
0x80090ba4: strh r6, [r11, #8]
0x80090ba8: b 0x80090bd4
0x80090bac: strh r5, [r11, #8]
0x80090bb0: strh r2, [r11, #8]
0x80090bb4: strh r1, [r11, #8]
0x80090bb8: strh r6, [r11, #8]
0x80090bbc: b 0x80090bd4
0x80090bc0: strh r5, [r11, #8]
0x80090bc4: strh r3, [r11, #8]
0x80090bc8: strh r2, [r11, #8]
0x80090bcc: strh r1, [r11, #8]
0x80090bd0: strh r6, [r11, #8]
0x80090bd4: mov r6, #1 ; 0x1
0x80090bd8: orr r6, r6, #4 ; 0x4
0x80090bdc: mov r5, #0 ; 0x0
0x80090be0: ldr r7, [r11, #12]
0x80090be4: add r5, r5, #1 ; 0x1
0x80090be8: cmp r5, #65536 ; 0x10000
0x80090bec: beq 0x80090ab0
0x80090bf0: and r8, r7, r6
0x80090bf4: cmp r8, r6
0x80090bf8: bne 0x80090be0
0x80090bfc: mov r5, #0 ; 0x0
0x80090c00: ldr r7, [r11, #12]
0x80090c04: and r8, r7, #4 ; 0x4
0x80090c08: add r5, r5, #1 ; 0x1
0x80090c0c: cmp r5, #65536 ; 0x10000
0x80090c10: beq 0x80090ab0
0x80090c14: cmp r8, #4 ; 0x4
0x80090c18: ldreqh r0, [r11, #8]
0x80090c1c: beq 0x80090c00
0x80090c20: mov r1, r4
0x80090c24: ldmia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, pc}
*** start of ?
0x80090c28: stmdb sp!, {r2, r3, r4, r5, r6, r7, r8, r9, lr}
0x80090c2c: mov r5, r0
0x80090c30: mov r4, #0 ; 0x0
0x80090c34: mov r9, #8 ; 0x8
0x80090c38: bl 0x80090b4c
0x80090c3c: and r6, r5, #3 ; 0x3
0x80090c40: mul r7, r6, r9
0x80090c44: mov r8, r0, lsl r7
0x80090c48: orr r4, r4, r8
0x80090c4c: add r5, r5, #1 ; 0x1
0x80090c50: mov r0, r5
0x80090c54: bl 0x80090b4c
0x80090c58: and r6, r5, #3 ; 0x3
0x80090c5c: mul r7, r6, r9
0x80090c60: mov r8, r0, lsl r7
0x80090c64: orr r4, r4, r8
0x80090c68: subs r0, r6, #3 ; 0x3
0x80090c6c: add r5, r5, #1 ; 0x1
0x80090c70: bne 0x80090c50
0x80090c74: mov r0, r4
0x80090c78: ldmia sp!, {r2, r3, r4, r5, r6, r7, r8, r9, pc}
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