The naming might not be ideal, but the Min Line Spacing is meant to give
a DRC if both legs of the diff pair get too close. The gaps not only
control the spacing of the diff pair as they are routed but also define
when they are coupled. Uncoupling can occur by exceeding the gap values
and also by routing the two legs at a value less than either gap. All
spacing from a diff pair to any other object is still controlled in the
spacing cset.
If anyone is looking for a quick summary of diff pair constraints and
the specific changes in 15.2 (such as gaps by layer) you can check out
the following document:
<install_dir>\doc\PCBmigration15x\highSpeed.html
You can also get to this through the Help > Migration Guide menu in
Allegro - it's buried at the bottom. In there is a table showing diff
pair parameters and their priority based on where they're set. This
table is relevant the diff pair discussion from 2 weeks ago 3/10 -
3/11).
Regards,
Dennis Nagle
Cadence
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: Monday, March 21, 2005 6:01 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: differential spacing clearance specification
problem...
Hi Stephen,
Thanks! That did it. Luckily, that property gets set when I set "Line
Spacing/Min" in the Differential Pair worksheet in the Constraints
Manager, which makes it easy to add.
Their naming is certainly confusing, at least to me. They might want to
give some indication what they mean by "Line Spacing" in this context,
that it is actually the minimum acceptable gap (including any reduced
gap for "necking").
Regards,
Austin
-----Original Message-----
From: Feehan, Stephen [mailto:Stephen.Feehan@xxxxxxxxxxx]
Sent: Monday, March 21, 2005 3:03 PM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: differential spacing clearance specification
problem...
Hello Austin,
If you add a Diffp_min_space property = 4.5 mil it will clear the DRC.
This is a new constraint that was added in V15.2.
-Stephen
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: Monday, March 21, 2005 2:23 PM
To: PCB Forum Mailing List
Subject: [PCB_FORUM] differential spacing clearance specification
problem...
Hi,
I have set-up the following in Allegro 15.2:
Using the Constraint Manager spreadsheet, differential signals are
paired.
Line spacing and gap etc. are NOT specified in the spreadsheet, only
phase tolerance and uncoupled length.
In Constraints/Physical rule set I setup a Constraint Set Name
"100_OHM_DE"
and have set DiffPair primary gap to 4.5 mils.
In Constraints/Spacing rule set I setup a Constraint Set Name
"DIFF_SPACING"
and give a Line to Line spacing of 9 mils.
What my goal is here, is to have a differential gap of 4.5 mils, and a
differential pair to any other signal clearance of 9 mils.
I then set-up via the assignment table and constraint manager so that
these rules apply to the differential pair signals under General
Properties/Physical, using Constraint Sets-Physical & Spacing.
What I get are trace to trace DRC errors within a differential pair,
saying the target clearance is 9 mils, and there is only 4.5. There
should only be 4.5, and it should not be checking trace to trace
within the differential pair. What am I doing wrong? It *works*
right, in that I get a differential gap of 4.5, and I get a pair to
other signal spacing of 9, but I get the LL DRC errors.
Regards,
Austin
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