[PCB_FORUM] Re: bus naming
- From: "Baumstark Michael-EMB043" <M.Baumstark@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Tue, 14 Sep 2010 16:05:06 -0400
Hi Sam:
To my knowledge Cadence does not yet support the concept of net
bundling. Bundles, as defined with another major EDA tool vendor allows
a bundling of disparate or syntactically similar net names into a
singular grouping, similar to a bus, but more appropriately labeled as a
bundle of nets, or a/k/a a wiring harness. But in effect this is a very
effective enabler to make schematic IOs across multiple sheets, clean
and neat.
Would anybody else like to request Cadence to implement the Bundle
capability into Concept HDL? Please submit your enhancement request to
get it on the radar from multiple customer's needs.
I would not recommend that you use the Concept HDL Bussing feature for
your cluster of net names. From your first example net_name syntax, it
appears that you are working with 18 sets of differential pairs, per N
number of banks and the net naming convention that you are using is
intuitive. (As a syntax suggestion, use _P and _M as your net_name
suffix: this will enable you to create all these signals into
appropriate diff pairs in a single automated command by using convenient
and unique wildcard selection for your diff-pair definition action, and
you can still reserve the _N net name suffix convention to be applied on
Active Low signals. ) If you were to map these signals to a bussing
convention, "busname<bit_number>", I believe that the Bus_name and
vector bit number will prevail as the final net_name after the schematic
is packaged and the netlist is loaded into Allegro; thus negating the
effort of your explicit naming of nets in the first place. Nor would I
suggest that you group all the N lane lines and the P lane lines into
two busses. They are diff-pairs, right?
If it is any consolation, it is not mandatory to attach an off_sheet
connector to any signals entering/leaving any number of flat level
schematic sheets, so long as the various wires in the node have a
matching sig_name property on it. But neatness in schematic drawings and
old_school schematic convention, input, output, bi-dir. would still
encourage this as good engineering practice, perhaps mandatory for Govt.
contract applications. (But you definitely need an I/O port if your
signals traverse Hierarchy, else they need to be defined as Global
signals to bridge Hierarchical schematic sheets.)
Explicit net_naming is a good design practice, IMO.
Sincerely yours,
Michael Baumstark
Sr. Staff Electrical Engineer / PCB Design, CID+
Motorola - EMS - Worldwide Radio Solutions -
Astro - APTC/Physical Design Organization
8000 West Sunrise Blvd. Mail Stop: 1329
Plantation, FL USA 33322-9947
Intra: http://rprc.mot.com <http://rprc.mot.com/> ;
http://pcbadvisor.mot.com <http://pcbadvisor.mot.com/>
web: http://www.motorola.com <http://www.motorola.com/>
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________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of
sjchar3@xxxxxxxxxxxx
Sent: Monday, September 13, 2010 12:27 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] bus naming
Group:
I have a nets that go to multiple pages, the pages would look cleaner
using busses.
For each bank#, the L? goes from 0-17.
for instance:
bank0_io_L1n
bank0_io_L1p
bank0_io_L2n
bank0_io_L2p
Can i make this a single bus? And use 1 off-page connector?
or do i need to rename all nets bank0_io_ln1, bank0_io_ln2 and place all
n's on one bus and p's on a different bus..
I guess my other option is to put off-connector for each net.
Any input would be appreciated
Sam
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