[PCB_FORUM] Re: Relative delay and differential pairs...

  • From: "Austin Franklin" <austin@xxxxxxxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Mon, 14 Mar 2005 09:25:38 -0500

Hi Gerry,

I'll let you know if it causes any problems!

Regards,

Austin

> -----Original Message-----
> From: Gerry Meier [mailto:gerry.meier@xxxxxxxxxxxxxx]
> Sent: Monday, March 14, 2005 8:34 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Relative delay and differential pairs...
> 
> 
> Then Go for it 
> 
> 
>  Gerry Meier 
> Sr. PCB Designer 
> Freedom CAD Services, Inc. 
> Voice: (603) 864-1300 x1350 
> Alt. Voice: (386) 753-0048 
> Email: gerry.meier@xxxxxxxxxxxxxx 
> visit our website at<http://www.freedomcad.com 
> 
> 
> -----Original Message-----
> From: Austin Franklin [mailto:austin@xxxxxxxxxxxx] 
> Sent: Monday, March 14, 2005 8:03 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Relative delay and differential pairs...
> 
> Hi Gerry,
> 
> > It's so easy to put both in the match group why bother not too.
> 
> Sure, but if it isn't needed, why do it?  I'd prefer to not have
> multiple constraints that aren't needed.
> 
> > If you only apply it to one which one?
> 
> It shouldn't matter.
> 
> > Is the same net always going to
> > be the shortest in the pair? Etc?
> 
> The other phase of the signal will follow it's "mate" with the phase
> tolerance constraint, so I don't see how that would matter.  Do you have
> an example in mind of what you believe is a potential problem with only
> specifying one phase?
> 
> Regards,
> 
> Austin
> 
> > -----Original Message-----
> > From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
> > Sent: Sunday, March 13, 2005 11:43 PM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
> > Subject: [PCB_FORUM] Relative delay and differential pairs...
> >
> > Hi,
> >
> > Do you guys specify the 2nd leg of the differential pair in a match 
> > group?
> > If so, what would the reason be?  I am assuming I only have to specify
> 
> > one leg of a DP in a match group and the other leg will be handled by 
> > the phase tolerance constraint established in the DP rules.  Is this 
> > correct?
> >
> > Regards,
> >
> > Austin
> 
> 
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