[PCB_FORUM] Prop Delay not seeing all the net

  • From: Dave Seymour <deseymour-pcb@xxxxxxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Wed, 2 Mar 2005 17:57:36 -0500 (GMT-05:00)

15.2

Anyone know why a DRC is generated when the entire
net length is correct? 

The net length is supposed to be between 2000 and 2500 mils.  

Probing the net gives --->Total Etch Length:      2280.31 MIL. 
Very good.

When the DRC is probed, only a portion of the net is reported.
Actual value:     1032.65 MIL
Very Bad.

What up with that?

I did check the box for in the user setup for pre 11.x checking.

Thanks for the help.
dave

LISTING: 1 element(s)

              < NET >

  Net Name:       CPU_CLK6

  Via Count:              3
  Total Etch Length:      2280.31 MIL
  Total Manhattan Length: 2257.7 MIL
  Percent Manhattan:      101.00%

  Pin                     Type      SigNoise Model
  ---                     ----      --------------
  R93.2                   BI        CDSDefaultIO
  J5.A13                  BI        CDSDefaultIO
  U4.27                   IN        CDSDefaultInput

  No connections remaining

  Properties attached to net
    CLASS             = CPU_CLK
    NET_SPACING_TYPE  = CLOCK
    NO_GLOSS
    MANUAL_ROUTES
    PROPAGATION_DELAY = AD:AR:2000 MIL:2500 MIL



LISTING: 1 element(s)

           < DRC ERROR >

  Class:           DRC ERROR CLASS
  Subclass:        ALL
  Origin xy:       (2083.30 -790.00)

  CONSTRAINT:      Propagation Delay
  CONSTRAINT SET:  PROPAGATION_DELAY
  CONSTRAINT TYPE: ATTRIBUTE
    Constraint value: AD:AR:2000 MIL:2500 MIL
    Actual value:     1032.65 MIL

-- 
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560

Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297

Dave.seymour@xxxxxxxxxxxx


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