[PCB_FORUM] Re: Enviroment Variable
- From: "Peter Hughes" <phughes@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 19 Mar 2007 15:59:44 -0000
Julian,
We had similar problems with our memory and this variable helped to fix
most but not all of these problems. The frequency with which we are
getting problems with the reuse of ECSets has decreased.
Rgrds
Peter Hughes,
PCB Designer,
Concurrent Technologies,
4 Gilberd Close,
Newcomen Way,
Colchester,
Essex,
CO4 4WN.
Tel: +44 1206 752626
Fax: +44 1206 751116
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: 19 March 2007 15:52
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable
I'll give you an example:
You have a CPU (U10) and a 5 memory chips (U1, U2, U3, U4 and U5).
You route the ADDRESS from U10 to U1, U2, U3, U4, and U5 in this
order.
You want to reuse this topology for another CPU-mem block. When you
apply the topology to this new circuit,
You get a ET error because the tools thinks that you should route the
equivalent of U10 to U1, U3, U2, U4, U5.
Although the traces and the memory chips are the same you are getting an
error.
Because the mapping is not the way you think it should be but the way
Allegro wants.
Julian
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Monday, March 19, 2007 8:43 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable
What exactly do you mean by mapping errors?
Jerry
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: Monday, March 19, 2007 11:28 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable
Will that fix mapping errors?
Julian
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Monday, March 19, 2007 7:58 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable
set update_ecset_refdes
Jerry
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]
Sent: Monday, March 19, 2007 10:54 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Enviroment Variable
Hi All,
Does anyone out there remember what the environment variable you can set
is, so that when you renumber a PCB the ECSet topologies will renumber
as well.
Rgrds
Peter Hughes,
PCB Designer,
Concurrent Technologies,
4 Gilberd Close,
Newcomen Way,
Colchester,
Essex,
CO4 4WN.
Tel: +44 1206 752626
Fax: +44 1206 751116
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