[PCB_FORUM] Re: ERROR 178 Message
- From: Jerry Grzenia <geraldg@xxxxxxxxxxx>
- To: "icu-pcb-forum@xxxxxxxxxxxxx" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 30 Mar 2011 14:00:29 -0700
Hi,
Go to the folder where the part exists. You'll see an entity folder there.
Delete this folder.
Then, in DEHDL, open the symbol view for the part and save it.
These Cadence Online Support Solutions might also help:
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=/concepthdl/concepthdl15.1/netlisterrors.html#1036243
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11189012
ERROR 178: Port exists in the entity but not on the instantiated symbol. Please
rewrite the necessary pages.
Description
The entity declaration for the instance (/entity/verilog.v or /entity/vhdl.vhd
file) declares a port that is not present on the symbol for the instance.
Solution
Open the symbol for the component in Concept HDL or Part Developer and add the
port on the symbol, if required. Then save the symbol. This will bring your
symbol and entity ports in sync.
To save the symbol in Concept HDL, do the following:
1. In Concept HDL, choose File > Open.
The View Open dialog box appears.
1. Select the library in which the component exists in the Library drop-down.
The list of components in the library are displayed.
1. Select the component for which the error occurred.
The component name is displayed in the Cell field.
1. Select Symbol from the View drop-down.
1. Click Open to view the symbol in Concept HDL.
1. Choose File > Save.
See if the error is eliminated.
Jerry
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Carrow, Dennis
Sent: Wednesday, March 30, 2011 3:47 PM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] ERROR 178 Message
Hello All,
I created a schematic symbol using Part Developer and when I place
it on the schematic and try to save it I get the following error:
ERROR 178: Port exists in the entity but not on the instantiated symbol. Please
rewrite the necessary pages.
Can someone tell me what stupid thing I obviously did to get this error?
Thanks for any help! -DC
Oh, using 16.3 Allegro Design Entry HDL...
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