[ibis] Re: High Current in the Power Clamp Curves
- From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
- To: "manish.bansal@xxxxxx" <manish.bansal@xxxxxx>, "'ibis@xxxxxxxxxxxxx'" <ibis@xxxxxxxxxxxxx>, "ibis-users@xxxxxxxxxxxxx" <ibis-users@xxxxxxxxxxxxx>
- Date: Wed, 27 Jan 2021 13:59:09 +0000
Manish,
The purpose of the clamp curves is to do just what they suggest, clamp the
voltage to the operating range. The curve you show looks like the combination
of GND Clamp and Power Clamp curves. The section of curve that you circled
shows that if the voltage at the pin would rise above 2.6V because of
reflections (or any reason, really) then the clamping diode conducts and draws
current to keep the voltage close to 2.6V. At about 3.5V the current increases
to cause an even harder clamping of the pin voltage to keep it from going
higher.
The result in simulation is that the pin voltage will almost never (still
possible) go above 3.5V. If you have a well-behaved signal to start with, which
stays below 2.5V anyway, the clamp curve will not change the result.
Regards,
Weston
From: ibis-users-bounce@xxxxxxxxxxxxx [mailto:ibis-users-bounce@xxxxxxxxxxxxx] ;
On Behalf Of Manish-FTM Bansal
Sent: Wednesday, January 27, 2021 7:46 AM
To: 'ibis@xxxxxxxxxxxxx' <ibis@xxxxxxxxxxxxx>; ibis-users@xxxxxxxxxxxxx
Subject: [ibis-users] High Current in the Power Clamp Curves
Dear Experts,
I need your opinion around following IBIS query.
In one of our IBIS model file, a very high clamp current is observed when PAD
voltage is swept from +V to +2V range as heighted in the waveform.
We would like to understand, what will be the potential impact of this high
current during board level Simulation ? or any other SOC/board level SI
analysis ?
Snapshot is attached :
[cid:image002.jpg@01D6F482.48E1ED20]
Regards,
Manish
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