[ibis] Agenda, European IBIS Summit Meeting at IEEE SPI 2018
- From: Mike LaBonte <mlabonte@xxxxxxxxxx>
- To: <ibis@xxxxxxxxxxxxx>, <ibis-users@xxxxxxxxxxxxx>
- Date: Fri, 11 May 2018 16:24:06 -0400 (EDT)
European IBIS Summit at IEEE SPI 2018
Agenda
The European IBIS Summit Meeting at IEEE SPI 2018 will be held Friday, May
25, agenda found below.
If you have not yet registered for the summit but plan to attend, please
see the registration information below. Presentation materials will be
available on-line during the event.
Many thanks to our co-sponsors Mentor, SiSoft, Teraspeed Labs, and Zuken.
Mike LaBonte, SiSoft
Chair, IBIS Open Forum
_____
European IBIS Summit at IEEE SPI 2018
_____
DATE:
Friday, May 25, 2018
TIME:
1:30 PM to 6:00 PM
LOCATION:
Le Quartz
Square Beethoven, 60 Rue du Château, 29210
Brest, France
ROOM:
Meridienne
CONTENT:
Presentations and Discussions
COST:
FREE
SPONSORS:
IBIS Open Forum
Mentor, a Siemens Business
SiSoft
Teraspeed Labs
Zuken GmbH
SPI 2018:
22-25 May 2018 <https://spi2018.sciencesconf.org/>
_____
<https://spi2018.sciencesconf.org/>
<https://spi2018.sciencesconf.org/>
_____
AGENDA
13:30
REFRESHMENTS AND SIGN IN
13:45
WELCOME AND INTRODUCTIONS
Mike LABONTE; SiSoft (USA)
14:00
IBIS Update
Mike LABONTE; SiSoft (USA)
14:20
IBIS-Compatible Macromodel and Interconnect Simulation Techniques
Jose SCHUTT-AINE; University of Illinois, Urbana-Champaign (USA)
14:40
On Automated Generation of Behavioral Parameterized Macromodels
Part I: Algorithmic Aspects
Tommaso BRADDE, Stefano GRIVET-TALOCIA, Marco DE STEFANO, Alessandro
ZANCO; Politecnico di Torino (Italy)
[Presented by Tommaso BRADDE; Politecnico di Torino (Italy)]
14:50
On Automated Generation of Behavioral Parameterized Macromodels
Part II: SPICE Equivalents and Applications
Marco DE STEFANO, Stefano GRIVET-TALOCIA, Tommaso BRADDE, Alessandro
ZANCO; Politecnico di Torino (Italy)
[Presented by Marco DE STEFANO; Politecnico di Torino (Italy)]
15:40
BREAK, REFRESHMENTS (20 Minutes)
16:00
IBIS-AMI and Jitter
Mike LABONTE; SiSoft (USA)
16:35
DDR5 Equalization Options with IBIS
Arpad MURANYI, Nitin BHAGWATH; Mentor, A Siemens Business (USA)
[Presented by Nitin BHAGWATH; Mentor, A Siemens Business (USA)]
17:10
IBIS [Model Selector] Improvement Proposal
Michael SCHAEDER*, Bob ROSS**; Zuken (Germany)*, Teraspeed Labs (USA)**
[Presented by Michael SCHAEDER; Zuken (Germany)]
17:30
OPEN DISCUSSION
17:50
CLOSING REMARKS
Mike LABONTE; SiSoft (USA)
17:55
END OF MEETING
18:00
AFTER MEETING BONUS: WALKING TOUR OF LOCAL HISTORICAL SITES
Mihai TELESCU; Université de Bretagne Occidentale, Brest (France)
_____
People involved in IBIS Model development, EDA tool development, and
digital circuit design are invited to participate. If you wish to
participate, please register with the information below:
Name:
E-mail address:
Company:
Send to:
Lance Wang (lwang@xxxxxxxxxx <mailto:lwang@xxxxxxxxxx> )
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