I noticed the discussion about terminator models for analog functions on ICs. We do this routinely for several reasons: It allows the simulator to include the analog nets in crosstalk simulations. The user gets a first order look at induced noise in analog nets. Customers have requested this "feature". For NC pins we will include terminator models so that users can run traces through these pads and pick up the associated pin parasitics in the simulations. Yes, some companies actually recommend running traces through no connect pins for their ICs. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@xxxxxxxxxxxxx www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 -----Original Message----- From: ibis-quality-bounce@xxxxxxxxxxxxx [mailto:ibis-quality-bounce@xxxxxxxxxxxxx] On Behalf Of Mike LaBonte (milabont) Sent: Monday, April 16, 2007 1:50 PM To: ibis-quality@xxxxxxxxxxxxx Subject: [ibis-quality] Minutes from the 10 Apr 2007 ibis-quality meeting Minutes from the 10 Apr 2007 ibis-quality meeting are attached. ARs: AR: Kim write new language adding 3.1.4 recommendations to 3.1.2 AR: Mike update spec with Kim's input, remove 3.1.4 AR: Mike update 3.2.1 to be less prescriptive for analog pins. Mike --------------------------------------------------------------------- IBIS Quality website: http://www.eda.org/pub/ibis/quality_wip/ IBIS Quality archives: //www.freelists.org/archives/ibis-quality To unsubscribe send an email: To: ibis-quality-request@xxxxxxxxxxxxx Subject: unsubscribe