[ibis-macro] Re: What I learned at DesignCon about PDN simulations.
- From: Cristian Filip <cris_filip2002@xxxxxxxx>
- To: "msteinb@xxxxxxxxxx" <msteinb@xxxxxxxxxx>, "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 5 Feb 2014 17:09:58 -0800 (PST)
Hi Mike,
This is a great answer and I am glad that I asked the question. It is always
good to learn from others. I will read the thesis.
Thank you,
Cristian
________________________________
From: Mike Steinberger <msteinb@xxxxxxxxxx>
To: ibis-macro@xxxxxxxxxxxxx
Sent: Wednesday, February 5, 2014 8:03:57 PM
Subject: [ibis-macro] Re: What I learned at DesignCon about PDN simulations.
Cristian-
Against my better judgement, I'm going to attempt to contribute to a
conversation that is poorly bounded, and can therefore quickly get out of hand.
I would take it kindly if we could avoid validating my assessment of this
conversation.
While this is far from a complete answer to your question, there's a
little-known body of measured data that lends insight to the topic at hand.
I suggest you read the dissertation of Dr. James Weaver, Stanford 2007.
http://vlsiweb.stanford.edu/papers/Released_Draft_rev2.pdf
Mike Steinberger
On 02/05/2014 06:40 PM, Cristian Filip wrote:
Hi Walter,
>Interesting discussion! The following two sentences in your comment are
>reviving for me a past debate on the PI topic:
>“The systems integrator does need to insure that he has sufficient bypass
>capacitors and power distribution on the board to supply current to the
>package. This is a ~25MegHz problem, not a ~GHz problem required by the
>chip/package tool.”
>The posts that I am referring to have the subject line “PI resonance test” and
>the debate took place around Jan. 20, 2014. At that time I suggested that the
>systems integrator task is to make sure that the board PDN is resonance free
>up to about 80 to 100 MHz. The PI experts on this forum have quickly corrected
>me and have suggested that this limit should be much higher (over 600 MHz),
>but nobody has really provided any upper limit. Now I am getting confused
>again and I am wondering if there is any consensus on this cutoff frequency
>limit among the industry experts or if it is left to everyone’s interpretation
>as “it always depends”. Could you please provide your own view on this matter?
>Thank you,
>Cristian
>
>
>From: Walter Katz mailto:wkatz@xxxxxxxxxx
>To: Bradley Brim mailto:bradb@xxxxxxxxxxx; IBIS-ATM
>mailto:ibis-macro@xxxxxxxxxxxxx
>Sent: Tuesday, February 4, 2014 8:22:13 AM
>Subject: [ibis-macro] Re: What I learned at DesignCon about PDN simulations.
>
>
>
>Brad,
>
>Again, your points are well taken. First, parallel interfaces are now
>exceeding 2GBps. Although S parameters might be overkill at these data rates,
>there are IC Vendors who are using “swathing” techniques for parallel
>interfaces with parameterized SPICE circuits. 11-WE7 would have been an ideal
>forum, but there was only enough time for one or two questions at the end. SSO
>analysis is important – the current state of the art is to include this noise
>in added timing margins and noise margins. So the answer is yes, I believe
>that IBIS should be including SSO macro models, but this traditionally has
>been beyond the scope of “Buffer” models. So to answer your question, yes
>IBIS-AIM (or another IBIS AdHoc committee would be an excellent forum for
>discussing adding PDN macro modeling to the IBIS standard.
>
>Walter
>
>From:Bradley Brim [mailto:bradb@xxxxxxxxxxx]
>Sent: Monday, February 03, 2014 11:40 PM
>To: wkatz@xxxxxxxxxx; IBIS-ATM
>Subject: RE: What I learned at DesignCon about PDN simulations.
>
>Hi Walter,
>
>Interested to learn in more detail your perception of requirements by “system
>integrators” for PDN and power-aware SI design. Does you comment apply to both
>serdes and parallel bus designs? DesignCon 2014 panel session 11-WE7 would
>have been an ideal forum in which to discuss this topic.
>
>Does your text below imply you believe system integrators only require enough
>information to select and place PCB decaps that are effective to ~25MHz. You
>seem to imply there is no need (nor available info or tools) for system
>integrators to pursue analyses such as SSO and performance for this should be
>assured apriori by packaged device vendors. If this is the case, seems
>difficult for system integrators to characterize their designs for noise
>margin compliance. Maybe you propose some form of PDN macromodel noise
>specification and a manner in which to include this in power-aware SI
>verification analyses? If so, an interesting idea. Has such been proposed or
>presented previously (e.g. at DesignCon) that you can cite for us? Seems a
>perfect topic for a few DesignCon tracks: system, PI or PCB.
>
>What is your goal in initiating the discussion with IBIS-ATM? Maybe a PDN
>macromodel specification as part of IBIS? If it’s not already established in
>the literature is ATM the proper forum to propose and prove-out such PDN
>macromodel approach?
>
>Cheers,
>-Brad
>
>From:ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
>On Behalf Of Walter Katz
>Sent: Monday, February 03, 2014 10:35 AM
>To: IBIS-ATM
>Subject: [ibis-macro] What I learned at DesignCon about PDN simulations.
>
>All,
>
>There were a large number of papers at DesignCon about PDN, and all pretty
>much said the same thing – it is all now a Science Experiment. Although the
>composite current now in IBIS is part of the solution, the real problem is how
>to apply composite current on all the buffers to determine the current
>requirements on chip. One needs both the spectral content of the total current
>on each rail and the phase (i.e. what buffers are transitioning when). A
>SerDes bus will normally have all Tx transitioning at more or less random
>times. This is assured by the data patterns being 8B10, or scrambled. DDR DQ
>memory busses can have more regular patterns (e.g. sending lots of 0 data with
>bursts of all 1’s or random data. This gets even more complicated for chips
>used in Mobile devices where whole sections of a chip can be turned on or off
>to conserve power. These problems need to be addressed by having sufficient
>on-die rail capacitance and sufficient package
capacitance. In addition, there needs to be sufficient capacitors on the
board. This on-die and package capacitance requirements need to be addressed by
the IC Vendor, requiring very detailed knowledge of the current requirements
for each buffer (e.g. IBIS composite current), detailed knowledge of the
spectral density and phase of the buffer switching, and detailed power models
on-die and in package. The systems integrator will not have access to this type
of information or the simulation tools required to do these types of analysis.
The systems integrator does need to insure that he has sufficient bypass
capacitors and power distribution on the board to supply current to the
package. This is a ~25MegHz problem, not a ~GHz problem required by the
chip/package tool.
>
>The bottom line is that we should not confuse the PDN modeling requirements of
>the Chip/Package tools and the PDN modeling requirements for the System
>Integrator.
>
>Walter
>
>Walter Katz
>wkatz@xxxxxxxxxx
>Phone 303.449-2308
>Mobile 303.335-6156
>
>
>
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