[ibis-macro] Re: Test Cases for IBIS Next (or whatever we decide to call it)
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 28 Aug 2012 21:42:29 +0000
Greg,
Thanks for volunteering in supplying models for this
experiment.
Since we are discussing package and on-die interconnect
modeling, I would think that we could assume that we
don't need to worry about AMI models in this experiment.
I would also think that we could assume just plain vanilla
buffer models (at least initially).
So I would suggest to start your examples with package and
if you have any, on-die interconnect models. I don't think
that the data in these models have to be "true", i.e. you
don't need to get into the NDA territory, but it should be
realistic enough to illustrate the usual modeling practices
you have.
Thanks,
Arpad
==============================================================
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Gregory R Edlund
Sent: Tuesday, August 28, 2012 3:19 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Test Cases for IBIS Next (or whatever we decide to call
it)
OK, guys. What would the EDA vendors like to see as examples? Both silicon
and package? Or just package? AMI or garden-variety IBIS?
Here are the variations I can come up with for a flip-chip BGA package:
1. single-ended
2. differential
3. uncoupled
4. coupled
5. T-line
6. vias
7. signal
8. power
9. s-parameters
10. lumped elements
Let me know if there is anything I'm missing.
Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N Bldg 050-3
Rochester, MN 55901
Other related posts:
