[ibis-macro] Minutes from Sep 2011 ibis-atm meetings
- From: Mike LaBonte <mike@xxxxxxxxxxx>
- To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
- Date: Sun, 25 Sep 2011 11:46:21 -0400
Minutes from Sep 2011 ibis-atm meetings are attached.
Mike
IBIS Macromodel Task Group
Meeting date: 20 Sep 2011
Members (asterisk for those attending):
Agilent: Fangyi Rao
* Radek Biernacki
Altera: * David Banas
Ansys: Samuel Mertens
* Dan Dvorscak
* Curtis Clark
Arrow Electronics: Ian Dodd
Cadence Design Systems: Terry Jernberg
* Ambrish Varma
Celsionix: Kellee Crisafulli
Cisco Systems: Ashwin Vasudevan
Syed Huq
Ericsson: Anders Ekholm
IBM: * Greg Edlund
Intel: Michael Mirmak
LSI Logic: Wenyi Jin
Mentor Graphics: * John Angulo
Zhen Mu
* Arpad Muranyi
Vladimir Dmitriev-Zdorov
Micron Technology: Randy Wolff
NetLogic Microsystems: Ryan Couts
Nokia-Siemens Networks: * Eckhard Lenski
QLogic Corp. * James Zhou
Sigrity: Brad Brim
Kumar Keshavan
Ken Willis
SiSoft: * Walter Katz
* Todd Westerhoff
Doug Burns
Snowbush IP: Marcus Van Ierssel
ST Micro: Syed Sadeghi
Teraspeed Consulting Group: Scott McMorrow
* Bob Ross
TI: Casey Morrison
Alfred Chong
Vitesse Semiconductor: Eric Sweetman
Xilinx: Mustansir Fanaswalla
unaffiliated: * Mike LaBonte
The meeting was lead by Todd Westerhoff
------------------------------------------------------------------------
Opens:
- None
--------------------------
Call for patent disclosure:
- None
-------------
Review of ARs:
- Walter update BIRD 123.2.4 and send to Mike for posting
- In progress
-------------
New Discussion:
Todd showed a presentation from Greg:
- Slide 2:
- Greg: Should we keep the terminator block on slide 2?
- Walter: We should not
- David: Does that mean not series pin in a TX model?
- Walter: Sometimes people add a termination to the buffer
- But it's really part of the buffer model
- David: It would be good to have terminator options instead of several
buffers
- Bob: One way to have terminations is through sub-models
- Todd: We usually need diff termination
- IBIS [Model] declarations are single ended
- Slide 3:
- Greg: The simulated PLL and CDR will model RX jitter
- Walter: This is accurate for stat
- For time domain CDR is in the ALG box
- Getwave usually does not have CDR in it
- Don't know if this is output or input to EQ2
- Kumar and Ambrish needed the files, no web client running
- Walter: We have a RX model of type Terminator
- Radek: That should be allowed
- Todd: If clock_ticks are not provided by the model, RX Clock_Recovery params
are used to provide a clock budget
- The main question is what point in the circuit jitter is injected
- Discussion of which parameters go where
- David: Why no TX voltage noise parameters?
- What protection would there be against disclosing jitter specifics?
- Is TX Rj from EDA tool to model or vice-versa?
- Is it from the user or from the model?
- Walter: It is from the model
- Kumar: RX Sj is modeled at the CDR
- The EDA tool should not add Sj
- David: How are refclk imperfections modeled?
- Todd: TX Rj is an Info param
- In the current BIRD the model is not expected to do anything with RX Sj
- It never sees the param
- BIRD 123 is about the EDA tool modulating clock_ticks
- Walter: When CDR does not include RX Sj DCD on refclk CDR ???
- If RX Sj is modeled in the algorithmic model's CDR it should not be an
info param
- Todd: New params can be created to tell the model how much Sj to generate
- Walter: It would have a new name, Model_Specific
- Todd: Does the simulator use only Info parameters?
- What if the DLL accepts an Input Rx_Sj parameter?
- Walter: It would be confusing if we overloaded that
- Arpad: The spec doesn't say that can't be done
- Mike: Slides 2 & 3 should have the jitter params annotated at the right places
Walter showed an email to explain Sj in BIRD 123.2.5:
- David: We need to specify this at multiple frequencies
- Walter: Fangyi brought that up
- A new BIRD would be needed for that
- Kumar: Would multiple instances of Sj do it?
- Walter: We would need something like a separate file or PDF
- Dual-Dirac has just 2 points
- In statistical mode a clock PDF might be adjusted
- David: Is it guaranteed simulators will observe clock_ticks?
- Walter: Yes
- Todd: Is there a difference between the simulator and the DLL modulating Sj?
- Kumar: The simulator will be more pessimistic
- The DLL will remove it
- Walter: At high freq the model might ask the EDA tool to do it
- Todd: Injecting at the latch and refclk are different
- Kumar: If the tool does the jittering it can't be tracked
- Walter: BUJ is jitter than the DLL can't model
- But it needs to be incorporated into the final result
- David: Why defend the request to the EDA tool to add jitter?
- Kumar: Often the CDR tracks jitter and takes it out
- Todd: It helps to know the physical basis of these jitters
- Power supply noise will not track out
- Walter: Anything that can't be tracked should be disclosed
- Todd: Is frequency required if RX Sj is specified?
- David: How is a simple magnitude of Sj helpful?
- That depends on how much goes into the CDR
- Walter: This is spread across all frequencies
- David; No CDR has a white noise jitter function
- Walter: It's a budget, which distribution should it be?
- We had discussed whether these should be Info or Out
- Amplitude noise changes with time where AGC is used
Meeting ended.
-------------
Next meeting: 27 Sep 2011 12:00pm PT
Next agenda:
1) Task list item discussions
-------------
IBIS Interconnect SPICE Wish List:
1) Simulator directives
IBIS Macromodel Task Group
Meeting date: 06 Sep 2011
Members (asterisk for those attending):
Agilent: Fangyi Rao
* Radek Biernacki
Altera: * David Banas
Ansys: Samuel Mertens
* Dan Dvorscak
* Curtis Clark
Arrow Electronics: Ian Dodd
Cadence Design Systems: Terry Jernberg
* Ambrish Varma
Celsionix: Kellee Crisafulli
Cisco Systems: Ashwin Vasudevan
Syed Huq
Ericsson: Anders Ekholm
IBM: * Greg Edlund
Intel: Michael Mirmak
LSI Logic: Wenyi Jin
Mentor Graphics: * John Angulo
Zhen Mu
* Arpad Muranyi
Vladimir Dmitriev-Zdorov
Micron Technology: Randy Wolff
NetLogic Microsystems: Ryan Couts
Nokia-Siemens Networks: * Eckhard Lenski
QLogic Corp. * James Zhou
Sigrity: Brad Brim
* Kumar Keshavan
* Ken Willis
SiSoft: * Walter Katz
* Todd Westerhoff
Doug Burns
Snowbush IP: Marcus Van Ierssel
ST Micro: Syed Sadeghi
Teraspeed Consulting Group: Scott McMorrow
* Bob Ross
TI: Casey Morrison
Alfred Chong
Vitesse Semiconductor: Eric Sweetman
Xilinx: Mustansir Fanaswalla
unaffiliated: * Mike LaBonte
The meeting was lead by Arpad Muranyi
------------------------------------------------------------------------
Opens:
- Arpad: Last week we discussed having an IBIS section on version differences
- Walter: IBIS 5.1 should only discuss AMI 5.1
- We should take a resolution to the Open Forum
- Arpad: We should have this on the agenda
- Greg Edlund wanted to show some slides on jitter
--------------------------
Call for patent disclosure:
- None
-------------
Review of ARs:
- Arpad: Inform Open Forum that BIRDs 137.1 and 143 will not change
- In progress
- Fangyi: to send suggestions on Jitter BIRD to Walter
- Done
- Walter: Send updated BIRDs 123.2.4 to Mike for posting
- Was sent to list
AR: Mike post latest BIRD 123.2.3 to ATM web
-------------
New Discussion:
Arpad showed BIRD 137.2:
- One minor typographical fix
- Arpad described the changes
- Bob: This is ready to go
- There should be discussion on how we deal with version changes
- Walter motioned to submit the BIRD to Open Forum
- Curtis seconded
AR: Arpad submit BIRD 137.2 to Open Forum
Arpad showed BIRD 143.1:
- This has the same changes as BIRD 137.2
- Arpad described the changes
- Walter motioned to submit the BIRD to Open Forum
- Curtis seconded
AR: Arpad submit BIRD 143.1 to Open Forum
Arpad showed BIRD 140.1:
- Arpad: This has new wording that Walter and I agreed to
- [External Model] and [External Circuit] have "corner_name"
- We only need to reference these names (Typ, Min, Max)
- This could have another paragraph about dependency tables
- We are not yet ready for that in this BIRD
- AMI have have to map to those names to 0, 1, 2
- Walter: EDA tools all have an intrinsic corner variable
- In one place Corner is a Format
- In another it's a parameter
- Bob: For Type String Corner would be quoted
- Walter described a Corner parameter
- Arpad: The question is if we want to untable this BIRD
- We can discuss next meeting
- Walter motioned to discuss BIRD 140.1 next meeting
- Bob and David seconded
- Ambrish asked if we should wait for dependency tables first
Arpad showed a slide presentation from Greg:
- Greg: Have been discussing AMY issues in Quality task group meetings
- Have been doing jab work to verify models
- Studying where jitter comes from
- Users will see a list of parameters but will not know know what they are
controlling
- BIRD 123 are jitter terms external to the DLL
- Walter; Rx_Noise is an exception
- Todd: That is still external to the DLL
- Slide 1:
- Greg explain the diagram
- Walter: The analog model is dashed
- The PKG is in there but it's usually in the IBIS file
- EQ may be between Pre and Out
- Greg: A 1 tap would have 2 parallel output stages
- Walter: That depends on how the TX is implemented
- Todd: EQ should be before Pre
- Walter: Replace Pre with EQ
- Todd:
- Arpad: What is the purpose of the Quality discussion?
- Greg: What does the DLL correspond to?
- Walter: The Pre
- Arpad changed Pre to EQ
- Todd: Jitter is only what comes out of the EQ box
- Ambrish: So no jitter can be in the model?
- Walter: It can't be in Init
- If it is Getwave the EDA tool must not add more jitter
- The refclk path is controlled by AVDD and VDD
- David: Can we tell the DLL what noise to assume?
- Walter: We have params to tell the EDA tool what the DLL models
- Todd: The block marked AMI should be Algorithmic
- Radek: The pkg is not part of the model?
- Walter: It is in IBIS
- Arpad: Those are often not good enough
- Ambrish: Will PKG affect IR?
- Todd: yes
- David: For FPGAs the PKG has to be kept separable
- Radek: The PKG is to be used if it is in the IBIS file
- Arpad made further block diagram changes
The call dropped saying that the chairperson disconnected. We resumed:
- Todd: When we say "model" it means to the edge of the die
-The analog channel includes all interconnect
- Walter: It also includes Term
- James: Where is the analog data saved?
- Walter: We know where the PKG and ALG models are
- The buffer analog in 5.0 is either IV/VT or [External Model]
- BIRD 122 proposes new AMI parameters to describe intrinsic models
- It will be something like a Thevenin or Touchstone model
- It might be ISS at some point
- The jitter could be internal or external to the AMI file
- James: Model makers have to provide TX DCD, etc.?
- Kumar: They only have to give corner values
- Walter: Model makers will know what jitter params are and are not included
- The ones not included must be parameters
- Radek: Users can not modify that
- Todd: If jitter is a range it implies the user can pick a number
- James: So users can change model jitter parameters?
- Walter: Users can select jitter if the model allows it
- Todd: Should users change AMI files?
- Kumar: Users do not have unlimited freedom to change AMI files?
- Walter: If IP is placed in different ICs the jitter changes
- James: The model maker can't know what the power supply is like
- Ambrish: Some jitter comes from the system
- The EDA tool has to add that
- Can the user add more DCD?
- Walter: Yes
- We should remove Out as an option for jitter params
- Kumar: If the AMI gives a range how will the user know he can add more jitter?
- Walter: The manual should give enough info
- Todd: The proposal is for the EDA tool to modulate stimulus
- The DLL can modify internally
- It can have an AMI that sets jitter to zero
- Users can edit that file
- Ambrish: What does the user do the add more system jitter
- Todd: If users do not edit AMI files the value can be a corner or range
- The EDA tool can still prompt for additional jitter
- James: The spec and EDA tool can do many things
- It's hard to know what it is actually doing though
- Todd: They may have trade secrets
- James: I need to know what is in and not in the model
- Todd: Anything handled by the DLL should be zero in the AMI file
- Walter: There will be a PS component that will be low frequency
- The EDA tool has to account for that
- James: Can we tell the user which parameters not to change?
- Walter: They should not change AMI files
- Ambrish: The EDA tool could handle it internally
- Todd: We have a model standard for ICs
- We can't tell and EDA tool what it can't do
- Greg: The DLL would have to model refclk jitter
- Walter: The DLL does not handle that
- It gets transition times
- Todd: It is modifying the output
- James: Walter was saying the opposite
- Walter: Transition times will have any jitter added by the tool
- Todd: Nothing on the table now talks about that refclk input
- Greg: This was an issue in the early days of PCIe
- Walter: They gave budgets for jitter at the output
- There was nothing at the inputs
- Now they have to describe jitter propagation
- It can't be a compliance test any more
- James: It is still not clear what the DLL is not doing
- Walter: It would be appropriate for the DLL to say what it's input should
include
- Ambrish: These models are supposed to be black box
- Todd: We can standardize how jitter is injected
- Models can be made with parameters that together model all jitter
- James: It should be clear that these jitter params do not mean the model
handles it
- Even for Rj
- Walter: There is a debate about Rj
- Applying it in time domain up front will not be accurate enough to get the
tails
- Post-processing may be better
- Walter read from BIRD 123 to clarify this
Slide 2 was not discussed
Meeting ended.
-------------
Next meeting: 6 Sep 2011 12:00pm PT
Next agenda:
1) Task list item discussions
-------------
IBIS Interconnect SPICE Wish List:
1) Simulator directives
IBIS Macromodel Task Group
Meeting date: 13 Sep 2011
Members (asterisk for those attending):
Agilent: * Fangyi Rao
* Radek Biernacki
Altera: * David Banas
Ansys: Samuel Mertens
* Dan Dvorscak
* Curtis Clark
Arrow Electronics: Ian Dodd
Cadence Design Systems: Terry Jernberg
* Ambrish Varma
Celsionix: Kellee Crisafulli
Cisco Systems: Ashwin Vasudevan
Syed Huq
Ericsson: Anders Ekholm
IBM: * Greg Edlund
Intel: Michael Mirmak
LSI Logic: Wenyi Jin
Mentor Graphics: * John Angulo
Zhen Mu
* Arpad Muranyi
Vladimir Dmitriev-Zdorov
Micron Technology: Randy Wolff
NetLogic Microsystems: Ryan Couts
Nokia-Siemens Networks: * Eckhard Lenski
QLogic Corp. * James Zhou
Sigrity: Brad Brim
* Kumar Keshavan
Ken Willis
SiSoft: Walter Katz
* Todd Westerhoff
Doug Burns
Snowbush IP: Marcus Van Ierssel
ST Micro: Syed Sadeghi
Teraspeed Consulting Group: Scott McMorrow
* Bob Ross
TI: Casey Morrison
Alfred Chong
Vitesse Semiconductor: Eric Sweetman
Xilinx: Mustansir Fanaswalla
unaffiliated: * Mike LaBonte
The meeting was lead by Arpad Muranyi
------------------------------------------------------------------------
Opens:
- Arpad: May have to leave soon, will leave meeting line open
- Greg will discuss jitter parameters
--------------------------
Call for patent disclosure:
- None
-------------
Review of ARs:
- Arpad submit BIRD 137.2 to Open Forum
- Done
- Arpad submit BIRD 143.1 to Open Forum
- Done
- Mike post latest BIRD 123.2.3 to ATM web
- Done just now 123.2.5
- Arpad: Inform Open Forum that BIRDs 137.1 and 143 will not change
- Done, will be discussed Friday
-------------
New Discussion:
Arpad showed BIRD 140.1:
- Arpad: Changes are near the bottom with **
- A_to_D and D_to_A have another column
- Has Format Corner specs
- Examples added
- New analysis added
- Radek: The official names of the corners are typ, min and max?
- Arpad: We might have to add mappings
- Radek: Min and max are OK, but we would want to avoid using slow and fast
- Arpad: We are really saying non-verbally what the mapping is
- Todd: In IBIS min means two things:
- For most params slow/weak
- For C_comp just the min value
- Tools like SPICE have more then 3 combinations
- I prefer slow/typ/fast
- Arpad: We can't change typ/min/max as the selector names
- Todd: It would be better to say min always means slow/weak except for C_comp
- Arpad: This BIRD is not written to solve that problem
- Ambrish: That one line should say typ/slow/fast
- Radek: If the model maker wants to use min and max values they will not use
Corner
- Arpad: In the first section we don't explain what Corner does
- Todd: I drop my objection
- Arpad is saying slow and fast are coming out of nowhere
- IBIS says what min and max mean
- Arpad just wants to extend that top AMI
- We will go beyond 3 corners
- The IBIS analog model can't go beyond 3 corners
- Arpad: Nothing keeps us from adding more columns
- Radek: Tying them together may be wrong for the future
- Ambrish: We would only have to add one line
- James: We should be able to do that
- The real issue is what min/max means
- Ambrish: We only have to point to section 9 paragraph 2
- James: It should be clear what the model maker did to create each column
- Arpad: Is this BIRD acceptable as is?
- We will continue this topic next week
Todd showed Greg's jitter parameter document:
- Greg: These are all external to the DLL?
- Todd: Agree
- Kumar: Disagree
- Assuming this is about BIRD 123
- Todd: This is about 5.0
- Kumar: RX Sj has to be handled by the CDR
- Also RX_Receiver_Sensitivity
- Todd: What does the simulator do if it's in the AMI
- Kumar: It depends on the model
- David: Does external mean the DLL gives the EDA tool options?
- Or does the tool tell the model how much it should be?
- It would not make sense for the tool to make up values
- Arpad: Only the model maker knows
- The tool should not have a say
- Todd showed the data format table
- Range allows any value within constraints
- David: It comes from the model maker to say what the silicon does
- Todd: Yes
- External means the DLL knows nothing about it
- The simulator is expected to do something
- Vih and Vil are handled that way
- David: "The model knows nothing about it" is confusing
- It implies the model maker did not provide it
- Kumar: These are often like eye mask parameters
- Todd: The RX is guiding the post-processing of data
- But the simulator handles it
- Arpad: Usually the outcome is an eye
- How does RX_Receiver_Sensitivity fit in?
- David: It gives what you need to define eye width
- Arpad: Is this a poor man's way to define eye mask?
- Usually Vinh and Vinl are used
- Todd: Anything between RX_RS would treated as impinging on an eye mask
- Fangyi: RX sens is used to calculate BER
- That is not device behavior
- The model should represent only device behavior
- The EDA tool has to use this
- Todd: The RX models delivers clock_times and waveform at the sample latch
- RX_RS tells us how to read the value there
- No part of IBIS specifies an eye mask
- Fangyi: The eye is not sufficient
- You have to know the model
- Todd: Yes several things are need to create an eye
- Todd slightly modified the first slide
Meeting ended.
-------------
Next meeting: 20 Sep 2011 12:00pm PT
Next agenda:
1) Task list item discussions
-------------
IBIS Interconnect SPICE Wish List:
1) Simulator directives
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- » [ibis-macro] Minutes from Sep 2011 ibis-atm meetings - Mike LaBonte
