Time: Tuesday, December 10, 2019 at Noon US Pacific Time
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WebEx:
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Upcoming meeting schedule:
December 17, 2019
December 24, 2019 - cancel
December 31, 2019 - cancel
January 7, 2020
January 14, 2020
January 21, 2020
January 28, 2020 - cancel (DesignCon)
February 4, 2020
Agenda
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1) Opens
- Today is the last meeting of the year... Thanks to everyone for
their participation and contributions!
2) Roll call
3) Review of ARs:
Walter: Prepare a draft a BIRD on based on the AMI_Impulse approach
- done
Bob: Submit BIRD197.6 to the IBIS Open Forum
- done
Mike L.: Make the changes as noted to BIRD181.2_draft1 and send it
out to the ATM reflector as BIRD181.2_draft2
- in progress?
Randy & Michael M.: Invite DDR memory and controller vendors to
comment on new protocols
- pending
Any other AR-s?
4) Call for any IBIS related patent disclosures
5) Approval of minutes
6) Review response from Japan on BIRD198 (All)
- discussion
7) Enabling Back Channel Interface in statistical mode (Walter)
- discussion on new draft
8) BIRD181.2_draft2 (Mike L.)
- discussion on new draft
9) Motion to adjourn?
Topic bin list:
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- IBIS-ISS parser
- Parameter directionality summary (Mike M.)
- Removing the single-ended input threshold requirements for
differential buffers (Mike M.?)
- Removing the single-ended characterization load requirements for
differential buffers (Mike M.?)
- Fix all the referencing problems in the current specification
(after Randy's C_comp proposal and BIRD189 are done)
(BIRD181.1 Bob, Mike L.)
- Guidance for power-aware vs. AMI models - do we have rules for
how a power-aware (and therefore potentially non-LTI) buffer
analog data set should be used with IBIS-AMI algorithmic data?
(important topic - 2018 ASIA IBIS Summit presentations)
(the spec. may not need to be changed for this)
- Digital signing of DLL/SO files. Should it be mentioned in the
spec, or required?
Tabled ARs:
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Randy: Investigate if/why/how a clock waveform input might be used
- in progress
Michael M.: Investigate if/why/how a clock waveform input might be used
- in progress
Michael M.: Check with IP experts on whether DC_Offset is useful for Tx
- in progress
Tabled topics:
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10) Jitter HF/LF components and Jitter Amplification (Mike M.)
- discussion
11) Other DDR5 related topics
- clock forwarding
- who generates the strobe (buffer model, or EDA tool)?
- buffer vs. component level modeling
- skew issues between control/address/data (component level)
- rise fall asymmetry
12) New BIRDs from Editorial Task Group? (Bob/Radek)
a) Specify buffer reference terminals for pins ([Pin Reference])
b) Simulation (aka DIA) vs. DUT (depends on #a)
c) C_comp and package reference in simulation clarifications
(depends on #a)
d) Make changes to the [Receiver Threshold], once a) and b) are
resolved
13) 166.4 Resolving problems with Redriver Init Flow (Walter)
14) BIRD190 (Ambrish)
15) Fangyi's Redriver flow BIRD draft (Fangyi)
- add equations
- consider rewriting the AMI "front end" in the spec (flows)
(when this proposal is added to the spec)
16) How to handle missing min/max data? (Arpad)
- what should be the governing rule for synchronizing
typ/min/max data?
Pending BIRDs awaiting discussion:
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166.4 Resolving problems with Redriver Init Flow
181.1 I/V Table Clarifications
190 Clarification for Redriver Flow
TBD New proposal for Redriver Flow (may replace BIRD166)
Thanks,
Arpad
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