This e-mail is to invite participation in the IBIS-ATM task group effort to
clean up the IBIS specification in the context of GROUND definition.
There were a few e-mail threads and preliminary discussions at both the ATM and
Interconnect task groups on this subject. The consensus is that the current
specification remains unclear in that respect. The plan is to have relatively
soon after Version 6.1 a new release of Version 6.2 that would be primarily
focused on this subject.
The purpose of the discussion is:
(1) to make clear statements regarding the global node "0",
(2) to make it clear what the reference node for the I/O signal ports is,
(3) to make it clear what the circuit topology is, e.g., C_comp and
[Package] connections,
(4) to make it clear what the coexistence of keywords like [Pulldown
Reference], [GND Clamp Reference] and [Pin Mapping] implies.
The clarification needs to cover multiple scenarios, both pre-layout and post
layout, ranging from single buffer simulation to multi-component simulation.
Background information
The original IBIS specification silently assumed that the reference node of the
I/O signal ports was the node GND. There is only one place in the description
of the node "A_gnd" (intended as the counterpart of GND) in the Multi-Lingual
Model Extension section which refers to "universal reference node, similar to
SPICE node 0". Otherwise there is no enforcement of using GND as the global
node "0", though starting with Version 5.1 some diagrams now show the global
node symbol. Nevertheless, particularly in simulation of a single buffer, or
multiple buffers where there is a common reference node, there is nothing wrong
to attach that reference node to the global node "0", either by the user or the
EDA tool. The only other place where the global node "0" can be present is an
IBIS-ISS subcircuit, if intentionally specified by the model vendor.
Consequences and limitation arising out of any such occurrences need to be
clarified.
Introduction of the [Pin Mapping] for power and ground bounce simulation and
the presence of the [Pulldown Reference] keyword established the presence of
the "Pulldown Reference" and "GND Clamp Reference" nodes but have not
identified clearly their relationship with respect to the signal I/O reference
node, or GND. It needs to be clearly stated what the signal I/O reference node
is. It is not only the "second" node in the I/O port, but also the common mode
port for the differential and pseudo-differential buffers. Furthermore, for the
pseudo-differential buffers, it is the connection node of the inverting and
non-inverting buffers.
Topics
The purpose of the discussion is to decide how the specification needs to
address the following questions. (Some answers are commonly understood, yet the
specification may need to unambiguously clarify it.) The list is not
exhaustive at this time.
1. Is the global node "0" assumed in any discussion or any diagram?
2. Under what circumstances the global node "0" can be used by the user
or the EDA tool?
3. What can be done if any IBIS-ISS subcircuit contains a global node "0"?
4. What nodes is the C_comp capacitance connected to?
5. What is the impact of different [Pulldown Reference] and [GND Clamp
Reference] values?
6. What is the relationship between non-zero [Pulldown Reference], [GND
Clamp Reference] and the signal I/O reference node in the absence of the [Pin
Mapping] keyword?
7. What is the relationship between non-zero [Pulldown Reference], [GND
Clamp Reference] and the signal I/O reference node when the [Pin Mapping]
keyword is present?
8. What is the relationship between pulldown_ref, and/or the
gnd_clamp_ref bus declaration under the [Pin Mapping] keyword and the signal
I/O reference node?
9. Do we need to extend the [Pin Mapping] definition to cover signal I/O
reference bus declaration?
We hope you can join our discussions and contribute to the clarification of the
GROUND issues in IBIS.
Radek
