I would like to un-table the [Pin Reference] BIRD, give the enclosed
presentation and discuss my alternative BIRD for referencing.
The first part of the presentation is basic physics, and requires that the
measurement of any voltage at an I/O buffer terminal be physically close
to the I/O buffer terminal. "physically close" is defined as 1/10
wavelength. The only nodes in any I/O buffer simulation that we are
assured to be close to the I/O buffer are the terminals of the buffer.
Mythical Node 0 and any global node that we call "Ground" cannot be used
as the reference voltage of an I/O buffer.
(Note that at today's speeds, wavelengths for DDR ~1", and SerDes are
~.1", so 1/10 of a wavelength is now approaching .01". Twenty years ago
wavelengths were 100", so we got away with being sloppy with GND.)
For a buffer with one Power rail terminal and one "GND" rail terminal and
one I/O terminal that gives us only two choices for the terminal to use as
a reference for the other two terminals. The obvious default should be the
terminal that is connected to the reference node of the test fixture when
the buffer is used to derive the IV, VT and model thresholds. This by
definition, is the rail terminal that has a [*** Reference]=0.0V.
In this presentation I propose using a new [Model] keyword [DUT Reference
Terminal] to specify which ***_Ref terminal should be used to override the
terminal that has [*** Reference]=0.0V, or the case when there is no [***
Note that if one uses the GND rail terminal as the reference node for all
I/O buffer terminal, we can arithmetically determine the voltage between
all of the terminals of the I/O buffer, particularly the voltage between
the I/O terminal and the Power rail terminal.
Determining these three voltage difference for the simple buffer with one
Power, GND and I/O terminal, is a totally separate issue on how to
interpret this voltage at the I/O with respect to the voltage thresholds
in the model when the voltage between the Power rail terminal and the GND
rail terminal during DIA is not the same as the voltages between these
terminal during DUT. [Receiver Thresholds] is one attempt to do this for
DDR interfaces. This issue has recently been referred to as scaling.
Scaling is a totally independent issue that does rely on a consistent way
of measuring the voltages at all of the terminals of the buffer.
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