[ibis-macro] August 23 Meeting Minutes
- From: "Todd Westerhoff (twesterh)" <twesterh@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 23 Aug 2005 16:24:43 -0400
meeting date: 23 aug 2005
attending: Arpad Muranyi, Todd Westerhoff, Ian Dodd, Bob Ross, Ken
Willis, Sam Chitwood
-------------
AR Review:
AR: Arpad continue work on library
==> New attachment for this meeting
AR: Ian find out if Mentor receiver can be public
==> In process
AR: All read "SPICE Compatibility" section of:
http://www.sisoft.com/ibis-macro/docs/verilog_ams_lrm_2.2.pdf
-------------
Arpad's new library additions:
- Charge-conserving capacitor, inductor can't be effectively
implemented because Verilog-AMS doesn't allow
parameters to me passed at run time.
- Ran into issues with DC operating point and transient simulations.
Section 5.3 of LRM discusses how values are retained
during simulation. Arpad worked through several iterations of
models before arriving at a set of equations that worked
across DC and transient conditions.
Mentor serial receiver:
- Mentor's model is based on work for a specific vendor, and Mentor
Marketing isn't comfortable sharing it.
- Ian agreed to define a generic high level template for a serial
receiver with clock recovery
AR: Ian to continue researching receiver architectures and come up with
a generic template
Verilog-AMS LRM / Spice compatibility
- Verilog-A discussions of Spice compatibility at Accelera have
dropped off
- Arpad will continue to monitor
Cadence macro-modeling templates
- Cadence wants to wait until after building block library is
complete to support pre-emphasis buffer
- Once pre-emphasis template and building blocks are complete,
Cadence will consider releasing additional templates
Passing parameters
- Verilog-A will not allow parameters to be passed at runtime. To
get around this, we can implement building blocks
that have an additional pin - a "control port" that passes a value
to be interpreted as a parameter. Do we want to
create building blocks like this?
AR: Arpad to post a note to the reflector to continue this discussion
What's missing in the current library
- Controlled sources
- Table-driven sources
- Triggerable (time-controlled) sources
- If/then/else equations
- Simulation time
- Previously computed values
- Calculation of 1st derivative of voltage or current
DesignCon IBIS Summit
- Current presentation plan is to review basic strategy (building
block library), outline the proposed contents of the
initial library, and show the pre-emphasis buffer from the previous
Summit, modified to call out the building blocks
from the standard library
- Arpad will continue work on the building block library and
reformatting the pre-emphasis buffer to call out data from
the library
- Todd/Mike to propose and develop paper for the IBIS Summit.
AR: Todd/Mike to propose paper for IBIS Summit and develop presentation
-------------
Next meeting: Tuesday August 23, 2005.
Todd Westerhoff
High Speed Design Group Manager
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719 email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
meeting date: 23 aug 2005
attending: Arpad Muranyi, Todd Westerhoff, Ian Dodd, Bob Ross, Ken Willis, Sam
Chitwood
-------------
AR Review:
AR: Arpad continue work on library
==> New attachement for this meeting
AR: Ian find out if Mentor receiver can be public
==> In process
AR: All read "SPICE Compatibility" section of:
http://www.sisoft.com/ibis-macro/docs/verilog_ams_lrm_2.2.pdf
-------------
Arpad's new library additions:
- Charge-conserving capacitor, inductor can't be effectively implemented
because Verilog-AMS doesn't allow
parameters to me passed at run time.
- Ran into issues with DC operating point and transient simulations.
Section 5.3 of LRM discusses how values are retained
during simulation. Arpad worked through serveral iterations of models
before arriving at a set of equations that worked
across DC and transient conditions.
Mentor serial receiver:
- Mentor's model is based on work for a specific vendor, amd Mentor
Marketing isn't comfortable sharing it.
- Ian agreed to define a generic high level template for a serial receiver
with clock recovery
AR: Ian to continue researching receiver architectures and come up with a
generic template
Verilog-AMS LRM / Spice compatibility
- Verilog-A discussions of Spice compatibility at Accelera have dropped off
- Arpad will contuinue to monitor
Cadence macro-modeling templates
- Cadence wants to wait until after building block library is complete to
support pre-emphasis buffer
- Once pre-emphasis template and building blocks are complete, Cadence will
consider releasing additional templates
Passing parameters
- Verilog-A will not allow parameters to be passed at runtime. To get
around this, we can implement building blocks
that have an additional pin - a "control port" that passes a value to be
interpreted as a parameter. Do we want to
create building blocks like this?
AR: Arpad to post a note to the reflector to continue this discussion
What's missing in the current library
- Controlled sources
- Table-driven sources
- Triggerable (time-controlled) sources
- If/then/else equations
- Simulation time
- Previously computed values
- Calculation of 1st derivative of voltage or current
DesignCon IBIS Summit
- Current presentation plan is to review basic strategy (building block
library), outline the proposed contents of the
intial library, and show the pre-emphasis buffer from the previous Summit,
modified to call out the building blocks
from the standard library
- Arpad will continue work on the building block library and reformatting
the pre-emphasis buffer to call out data from
the library
- Todd/Mike to propose and develop paper for the IBIS Summit.
AR: Todd/Mike to propose paper for IBIS Summit and develop presentation
-------------
Next meeting: Tuesday August 23, 2005.
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