[ibis-interconn] My AR's When are model Pre-layout and precedence
- From: Walter Katz <wkatz@xxxxxxxxxx>
- To: "IBIS-Interconnect" <ibis-interconn@xxxxxxxxxxxxx>
- Date: Wed, 8 Oct 2014 17:18:13 -0400 (EDT)
All
My two AR's:
1. We need a careful discussion on when package models are
Pre-Layout only. (Walter)
2. We need a careful discussion on precedence rules if more than one
model can be used to represent interconnect. (Walter)
a. Are you referring to legacy package models together with this new
package/interconnect model, or multiple new package/interconnect models?
Pre vs Post Layout Models
. A model is a "Post Layout" model when the I/O terminals can be
mapped to specific pin names. The terminals to supply (POWER and GND) pins
may explicitly reference specific pin names or POWER and GND signal_name.
Post Layout models. The terminals of Post Layout models may not be
referenced by Model_name or Default.
. A "Pre Layout" model has terminals that have a Terminal ID that
is either a Model_name or Default.
. For an interconnect model to be Post Layout it must explicitly
connect specific I/O pin(s) and a specific I/O buffers, and this can only
be done using Pin_name. By connecting the pin of a model_name to a buffer
of a model_name the connection can be between any pins and buffers where
the buffer has that model name, this this would be considered a Pre Layout
model. When using the "Default" option on terminals, the connection can be
between any pin and its corresponding buffer. This also is considered a
Pre Layout model.
Precedence
. The process for choosing a interconnect models is to start with
a list of all of the buffers that are being simulated and are in a single
component. The EDA tool may choose to pick a different package model for
each I/O Pin/Buffer pair, or find a package model for any group of
Pin/Buffer pairs. There shall be no specific rule if the EDA choose
different combinations of package models that will connect all of the
given pins and buffers. Generally it would be preferable to Post Layout
instead of Pre Layout interconnect models, and to pick models that include
highest percentage of the buffers being simulated. It is generally
preferable to choose interconnect models that Post Layout vs Pre Layout,
and Model then association by model_name and finally using Default. There
are other tradeoffs such as performance, crosstalk and power distribution
that will determine which models to use for specific simulations.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
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