[ibis-interconn] Minutes, Jan. 23 IBIS-Interconnect Task Group and Feb. 6, 2013 Agenda

  • From: "Mirmak, Michael" <michael.mirmak@xxxxxxxxx>
  • To: "IBIS-Interconnect (ibis-interconn@xxxxxxxxxxxxx)" <ibis-interconn@xxxxxxxxxxxxx>
  • Date: Wed, 6 Feb 2013 06:03:03 +0000

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IBIS INTERCONNECT TASK GROUP MEETING

http://www.eda.org/ibis/interconnect_wip/

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Next meeting: Feb. 6, 2013
8 AM US Pacific Time

Agenda:
Attendance
Call for Patents
Agenda and Opens
Review of Task Group Status after Summit, ATM Meeting
Next Meetings' Schedule/Agenda:
* Feb. 13
* Feb. 20

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Attendees, Jan. 23

Agilent Technologies            Radek Biernacki*
Altera                                          David Banas*
ANSYS                                           Luis Armenta, Steve Pytel
Cadence Design Systems                  Brad Brim, Ambrish Varma
Intel                                           Michael Mirmak*
Mentor Graphics                         Arpad Muranyi*
Micron Technology                       Justin Butterfield*, Randy Wolff*
QLogic                                          Jason Zhou
Signal Integrity Software               Walter Katz*
Teraspeed Consulting Group      Bob Ross*


Minutes
No patents were declared.  No opens were raised.

Michael Mirmak summarized the proposed Summit material from Walter Katz.  Bob 
Ross stated that the thrust of this presentation is EMD, which hasn't been 
discussed in a summit before.  Michael agreed, suggesting that a separate 
presentation on EMD would generate interest, discussion and expansion.  Another 
slide set would be provided to show Interconnect Task Group progress.

Walter suggested that the final/summary EMD slide be used as the introductory 
Task Group summary slide.  Walter suggests that a topology slide from a 
previous presentation from ANSYS to show issues facing the industry.  
Additionally, a list of presentations should be provided.  Michael volunteered 
to complete the slides and present them.

Walter requested that his document stating the relationship between "MCI" (a 
generic term) and EMD be posted to the web page.  He referred to a statement 
from Brad Brim regarding "MCI" as a tool for IC vendors to build an EMD file.  
It is unknown whether this applies to Si2 efforts or not.

Bob asked whether the Si2 efforts are still on-track.  Walter noted that the 
dividing line between on-die interconnect and the buffer model is the 
fundamental issue.

Walter pointed out the IBIS 5.1 limitation slide in his EMD presentation.  The 
relationship between the buffer and bump pad being a single point/node rather 
than the reality of a separation between the bump pad and the buffer.  For AMI, 
the common practice is to put this information into a Touchstone file; in AMI, 
there's no such thing as a high or low state (in contrast to [Model]).  Michael 
added that there's interaction between ATM and this group because of 
controversy regarding how that analog information is tied into AMI and [Model], 
including TX stimulus.  Walter stated that C. Kumar had earlier pointed out 
that the impulse response of the channel should not constrain how it is 
generated; the user can generate it any way he wants.  It wasn't clear though 
how to generate the analog models for the TX and the RX and how they interact 
with the impulse response.

Bob asked when you say "channel", this includes the package portion of the TX 
and RX and the interconnect?  Walter replied not, it also includes the analog 
model that the IC vendor says to use at both the TX and the RX.  If you are an 
IBIS person (as opposed to an S-parameter person), you need a [Model]; in any 
case, it must include the reactive portion of the TX and RX that will affect 
the generation of the TX and RX.  James's ATM comment was that the IC vendor 
decides where that point is in the silicon.  Walter wants to add to that that 
the algorithmic model is to the right and analog modeling is to the left.  The 
IC vendor has to supply the partial data; a classic example is a peaking 
filter, which is not reactive.  It can be in either section, but it can't be in 
both sections simultaneously.

Bob noted that one interpretation of AMI is that the IBIS AMI paths can be 
interpreted as separate or having separate paths than traditional IBIS.  Actual 
signals in analog AMI are representative, whereas the AMI flow may include a 
bit pattern beyond what a standard model provides .  Walter described a 
traditional two-tap TX approach with Driver Schedule and stimulus.  Nowadays 
hundreds of submodels would be needed to sequence modern buffers.

David Banas reported on his GetWave survey results - 9 total respondents; all 
but 1 answered "A" (input to analog channel); the sole discrepancy was Arpad 
Muranyi, who answered F.   Radek Biernacki noted that question A was not 100% 
precise; the intent was the combination of TX backend, package, interconnect 
channel, etc.; that could be interpreted differently, so answer F could be 
acceptable.  David replied that the group could use a good reference diagram.

Bob added that output of GetWave is to the input of the channel; therefore, 
that includes the TX analog model.  Radek replied that the convolution of a 
single output response is subject to actually being able to perform the 
convolution, so we need an ideal voltage source to drive the channel.  Those 
three pieces are driven by a voltage source, or at least something like one.  
Model makers decide where to put that point.  The output of GetWave needs to be 
convolved with impulse response.  Michael summarized responses he has received 
in the past on real number inputs to SPICE-style IBIS implementations.  Walter 
noted that this is the crux of the discrepancy between visions of the TX 
buffer: an S4P representation of buffer in SPICE vs. numerical calculation 
environment approach.

Radek asked, in analog simulators like SPICE, you need an analog source to 
drive the buffer; the intent, however, was to have a digital stimulus to toggle 
the buffer.  How is that implemented in an analog simulator?  With an analog 
source, the trigger events occur when you cross a threshold.  In *that* 
context, Radek agrees with Arpad.  The analog portion comes from how we have to 
handle the AMI simulations.  We are not clear on descriptions and relationships 
for all cases; if you have S4P, ports are clear, but if you have an IBIS 
buffer, it's not particularly clear.  Walter replied that the reason why 
5.0/5.1 is in fact correct for traditional models is because we are using IBIS 
with a step response and measuring/creating an impulse response for a 
*particular* voltage swing, the one that the buffer can supply to the rest of 
the channel.  AMI assumes LTI, so this impulse response can be scaled to match 
the actual response of GetWave.

David noted that four categories were identified: EDA, silicon vendor, 
consultant, ?;  5 EDA vendors, 2 vendors, 1 consultant, 1 ?.  On question 2, 
there were 5 answers for "normative", 2 answers for "informative"; 2 for a mix 
(on Section 10).   Walter summarized the differences between normative and 
informative.

David stated that a diagram will be sent out to stimulate discussion.  Walter 
observed that the derivation methods are in the specification; this is murky on 
informative vs. normative.  Walter suggests specific sections be labeled 
normative vs. informative; David seconds.

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  • » [ibis-interconn] Minutes, Jan. 23 IBIS-Interconnect Task Group and Feb. 6, 2013 Agenda - Mirmak, Michael