Walter,
Scott is absolutely correct. The catch is this statement:
"But, ground bounce inductance and resistance is then lumped into power
circuit and signal path circuits, and the discrimination between the these is
lost."
With that, the question becomes, how do we want to visualize
the results, and I feel that the answer is related to the
relativity theory. Do we want to see the dog wiggle its tail,
or the tail wiggle the dog... :)
More seriously, if we only care about how the receiver sees
the signal, we really don't need to know whether the receiver's
"GND" (i.e. reference) was rock steady or bouncing like crazy.
But if we want to make sure that the receiver's "GND" is not
bouncing like crazy, we will most likely want to see what it
does. But then the question becomes: "with respect to what?"...
Perhaps a better "GND" under the chip (GND plane of the PCB),
or the VRM half a mile away, or the ground stake at the utility
service entrance two miles away... :) I am trying to be funny
with some of this, but a package designer maybe serious about
wanting to know how good the GND traces are in his/her package...
Thanks,
Arpad
================================================================
From: ibis-editorial-bounce@xxxxxxxxxxxxx
[mailto:ibis-editorial-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Sunday, March 13, 2016 7:06 PM
To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>; ibis-interconn@xxxxxxxxxxxxx;
ibis-editorial@xxxxxxxxxxxxx
Subject: [ibis-editorial] According to Scott McMorrow the Node 0 ground
assumption can be valid!
All, (and Radek, Brad and Vladimir in particular)
Scott McMorrow writes:
Circuit theory says that we can go from a partial element system where ground
and power loops are fully modeled to a ground referenced system where node 0
ground is applied to every element in the path. But, ground bounce inductance
and resistance is then lumped into power circuit and signal path circuits, and
the discrimination between the these is lost. From a differential node voltage
perspective at the receiver, the result is the same. The voltage between the
signal and ground will remain the same. If there is a difference, then
somewhere in the circuit, the ground partial inductance has not been reduced
into the loop inductance for the signal path and power paths.
It is a pretty standard transformation from partial inductance/resistance
matrices to loop inductance/resistance matrices, and is covered quite
extensively in Brian Young's book, which is still the best on the subject. He's
been at Motorola and TI. I believe he's at TI now running their ASIC packaging
group.
http://www.amazon.com/Digital-Signal-Integrity-Simulation-Interconnects/dp/0130289043
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
Phone 303.449-2308
Mobile 303.335-6156