[ibis-editorial] Re: An editorial correction for 5.1
- From: "Mirmak, Michael" <michael.mirmak@xxxxxxxxx>
- To: "ibis-editorial@xxxxxxxxxxxxx" <ibis-editorial@xxxxxxxxxxxxx>
- Date: Thu, 11 Aug 2011 11:17:08 -0600
I believe we can fix these as editorial improvements, so long as the issues are
only in the examples.
- MM
-----Original Message-----
From: ibis-editorial-bounce@xxxxxxxxxxxxx
[mailto:ibis-editorial-bounce@xxxxxxxxxxxxx] On Behalf Of Muranyi, Arpad
Sent: Thursday, August 11, 2011 9:49 AM
To: ibis-editorial@xxxxxxxxxxxxx
Subject: [ibis-editorial] An editorial correction for 5.1
Hello everyone,
I just noticed something that I believe is a typographical error.
On pg. 119 we have this for the VHDL-AMS example:
| Corner corner_name file_name circuit_name entity(architecture)
The "circuit_name" seems to be a cut and paste left over from
the SPICE example. In VHDL-AMS files there is no such thing
as circuit name, there is only "entity(architecture)" name.
The "circuit_name" is an extra entry on this line. The three
lines following this header are correct, but notice that there
is only file name and entity(architecture) there...
I think the same goes for the Verilog-AMS example:
| Corner corner_name file_name circuit_name (module)
because in Verilog-AMS there is only module name, and no circuit
name. I am sure this appears in multiple places, which I didn't
have time to search out.
Is this something we can fix in this editorial process, or do I
need to write a BIRD for this?
Thanks,
Arpad
==================================================================
Other related posts:
