Hello Editorial Committee,
I discovered a few problems with the verbiage in the [External Model] and
[External Circuit]
sections, which we might want to address as an editorial correction.
Quoting from pg. 110:
"If at-pad measurements for a SPICE, IBIS-ISS, Verilog-A(MS) or VHDL-A(MS)
model are desired, the A_signal_pos port would be named in the A_to_D line
under port1 and A_signal_neg under port2. The A_to_D converter then effectively
acts "in parallel" with the load of the buffer circuit. If internal
measurements are desired (e.g., if the user wishes to view the signal after
processing by the input buffer), the user-defined analog signal port would be
named in the A_to_D line under port1."
Note that the paragraph begins with: "IMPORTANT: For true-differential buffers
under [External Model]...",
and the first part of the quoted text above talks about A_signal_pos/neg and
port1/2. While I realize that
the receiver model in [External Model] could have a single ended output, it
could just as easily have a
differential output. Consequently, the highlighted text should really address
both cases, single ended
output and differential output at the core side. For this reason it might be
useful to change the highlighted
above text to something along these lines:
"If at-pad measurements for a SPICE, IBIS-ISS, Verilog-A(MS) or VHDL-A(MS)
model are desired, the A_signal_pos port would be named in the A_to_D line
under port1 and A_signal_neg under port2. The A_to_D converter then effectively
acts "in parallel" with the load of the buffer circuit. If internal
measurements are desired (e.g., if the user wishes to view the signal after
processing by the input buffer), the ports in the A_to_D line would name either
two user-defined analog output signal port names if the input buffer's output
is differential, or one user-defined analog output signal port name and a
reserved or user-defined reference port name if the input buffer's output is
single ended."
The corresponding section on pg. 125 has the same problem in the highlighted
text at the end of the
following quote, but in addition to that, this section has another problem
because it uses "A_signal"
twice, while the spec states on pg. 123 that under the [External Circuit]
keyword only the digital
reserved port names have special meaning. The illustration in Figure 29 uses
"A_mysig" for the pad
side analog signal port name, so we should probably use something similar in
this text also. I would
suggest to change this text:
"However, for [External Circuit]s, the user may choose whether to measure the
analog input response in the usual fashion or internal to the circuit (this
does not preclude tools from reporting digital D_receive and/or analog
responses in addition to normal A_signal response). If native IBIS measurements
are desired, the A_signal port would be named in the A_to_D line under port1.
The A_to_D converter then effectively acts "in parallel" with the load of the
circuit. If internal measurements are desired (e.g., if the user wishes to view
the signal after processing by the receiver), the user-defined analog signal
port would be named in the A_to_D line under port1."
to something along these lines:
"However, for [External Circuit]s, the user may choose whether to measure the
analog input response in the usual fashion or internal to the circuit (this
does not preclude tools from reporting digital D_receive and/or analog
responses in addition to normal at-pad response). If native IBIS measurements
are desired, the ports in the A_to_D line would name either two user-defined
analog input signal port names if the input buffer is differential, or one
user-defined analog input signal port name and a user-defined reference port
name if the input buffer is single ended. The A_to_D converter then
effectively acts "in parallel" with the load of the circuit. If internal
measurements are desired (e.g., if the user wishes to view the signal after
processing by the receiver), the ports in the A_to_D line would name either two
user-defined analog output signal port names if the input buffer's output is
differential, or one user-defined analog output signal port name and a
user-defined reference port name if the input buffer's output is single ended."
In short, I would like to propose to change the yellow highlighted text to the
green
highlighted text. I hope this is not too much to do without a BIRD...
Questions,
comments welcome, as usual.
Thanks,
Arpad
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