[hhvm-ppc] Re: RIP Register and Instructions with Relative Address modes.

From: rogealve@xxxxxxxxxx
Date: Mon, 14 Sep 2015 14:22:34 -0300

I was analyzing the piece of code we need the instruction with RIP
Relative. I guess we can substitute the instruction with a baseless load
with the address. But we will have to create a switch to ppc64 arch. What
do you think?

void CodeGenerator::cgLdBindAddr(IRInstruction* inst) {
auto const extra = inst->extra<LdBindAddr>();
auto const dstReg = dstLoc(inst, 0).reg();
auto& v = vmain();

// Emit service request to smash address of SrcKey into 'addr'.
auto const addrPtr = mcg->allocData<TCA>(sizeof(TCA), 1);
v << bindaddr{addrPtr, extra->sk, extra->spOff};

// Load the maybe bound address.
auto const addr = reinterpret_cast<intptr_t>(addrPtr);
// the tc/global data is intentionally layed out to guarantee
// rip-relative addressing will work.
// Also, a rip-relative load, is 1 byte smaller than the corresponding
// baseless load.
v << loadqp{rip[addr], dstReg};
}

From: rogealve@xxxxxxxxxx
To: hhvm-ppc@xxxxxxxxxxxxx
Date: 09/10/2015 02:11 PM
Subject: [hhvm-ppc] Re: RIP Register and Instructions with Relative
Address modes.
Sent by: hhvm-ppc-bounce@xxxxxxxxxxxxx

Inactive hide details for "Gustavo Serra Scalet" ---09/10/2015 01:12:20
PM---> -----Original Message----- > From: hhvm-ppc-bou"Gustavo Serra
Scalet" ---09/10/2015 01:12:20 PM---> -----Original Message----- > From:
hhvm-ppc-bounce@xxxxxxxxxxxxx [mailto:hhvm-ppc-

From: "Gustavo Serra Scalet" <gustavo.scalet@xxxxxxxxxxxxxxx>
To: "hhvm-ppc@xxxxxxxxxxxxx" <hhvm-ppc@xxxxxxxxxxxxx>
Date: 09/10/2015 01:12 PM
Subject: [hhvm-ppc] Re: RIP Register and Instructions with Relative Address
modes.
Sent by: hhvm-ppc-bounce@xxxxxxxxxxxxx

Well it's a instruction pointer for the next instruction at least that's
what Intel says: "The 64-bit instruction pointer RIP points to the next
instruction to be executed, and supports a 64-bit flat memory model. Memory
address layout in current operating systems is covered later."

And about a RIP Relative Address that's what they said: "An effective
address is formed by adding displacement to the 64-bit RIP of the next
instruction."

I took it from there
https://software.intel.com/en-us/articles/introduction-to-x64-assembly and
the X64 Software develop material. Yes i know the LR holds return of
address only and my idea was manipulate that as we don't have access to NIP
or IAR register. About you idea of TOC (r2) usage can you explain this
better? i don't get it.

Thx

-----Original Message-----
From: hhvm-ppc-bounce@xxxxxxxxxxxxx [mailto:hhvm-ppc-
bounce@xxxxxxxxxxxxx] On Behalf Of rogealve@xxxxxxxxxx
Sent: quinta-feira, 10 de setembro de 2015 12:01
To: hhvm-ppc@xxxxxxxxxxxxx
Subject: [hhvm-ppc] RIP Register and Instructions with Relative Address
modes.

Hi everyone,

In X64 we have a RIP register who contains the instructions pointer (a
pointer to the next instruction).

Actually it's not a pointer to next instruction. The RIP is used as a
instruction pointer relative data access. E.g[1]:
mov rax, [addr] instruction moves 8 bytes beginning at addr + rip to rax.

For me this seems more like the TOC (r2) usage on ppc64, where we can
reference a global symbol directly by the offset from TOC table.

i'm thinking to use something Link
Register LR to get the current PC and increment this by 4 to get the
next instruction. Is there a problem with this approach?

Please don't manipulate LR like that. It should be used to store the return
address only.

[1] https://msdn.microsoft.com/en-us/library/windows/hardware/ff561499
(v=vs.85).aspx

References:
- [hhvm-ppc] RIP Register and Instructions with Relative Address modes.
  - From: rogealve
- [hhvm-ppc] Re: RIP Register and Instructions with Relative Address modes.
  - From: Gustavo Serra Scalet
- [hhvm-ppc] Re: RIP Register and Instructions with Relative Address modes.
  - From: rogealve

[hhvm-ppc] Re: RIP Register and Instructions with Relative Address modes.

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