[haiku-commits] r42852 - haiku/trunk/headers/private/graphics/intel_extreme
- From: mmlr@xxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Fri, 14 Oct 2011 22:15:33 +0200 (CEST)
Author: mmlr
Date: 2011-10-14 22:15:33 +0200 (Fri, 14 Oct 2011)
New Revision: 42852
Changeset: https://dev.haiku-os.org/changeset/42852
Modified:
haiku/trunk/headers/private/graphics/intel_extreme/intel_extreme.h
Log:
Group the PCH registers logically.
Modified: haiku/trunk/headers/private/graphics/intel_extreme/intel_extreme.h
===================================================================
--- haiku/trunk/headers/private/graphics/intel_extreme/intel_extreme.h
2011-10-14 19:30:20 UTC (rev 42851)
+++ haiku/trunk/headers/private/graphics/intel_extreme/intel_extreme.h
2011-10-14 20:15:33 UTC (rev 42852)
@@ -225,15 +225,20 @@
// to a PCH based one, that means anything that used to communicate via (G)MCH
// registers needs to use different ones on PCH based platforms (Ironlake and
// up, SandyBridge, etc.).
+
+// North Shared Functions
#define PCH_DE_POWER_MEASUREMENT 0x42400
#define PCH_DE_INTERRUPT_STATUS 0x44000 //
INTEL_INTERRUPT_STATUS
#define PCH_DE_INTERRUPT_MASK 0x44004 // INTEL_INTERRUPT_MASK
#define PCH_DE_INTERRUPT_IDENTITY 0x44008 //
INTEL_INTERRUPT_IDENTITY
#define PCH_DE_INTERRUPT_ENABLED 0x4400c //
INTEL_INTERRUPT_ENABLED
-#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 //
INTEL_DISPLAY_A_ANALOG_PORT
-#define PCH_DISPLAY_A_DIGITAL_PORT 0xe1120 //
INTEL_DISPLAY_A_DIGITAL_PORT
-#define PCH_DISPLAY_B_DIGITAL_PORT 0xe1140 //
INTEL_DISPLAY_B_DIGITAL_PORT
-#define PCH_DISPLAY_LVDS_PORT 0xe1180 //
INTEL_DISPLAY_LVDS_PORT
+#define PCH_DISPLAY_A_PALETTE 0x4a000 //
INTEL_DISPLAY_A_PALETTE
+#define PCH_DISPLAY_B_PALETTE 0x4a800 //
INTEL_DISPLAY_B_PALETTE
+
+#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7)
+#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15)
+
+// South Shared Functions
#define PCH_I2C_IO_A 0xc5010 //
INTEL_I2C_IO_A
#define PCH_I2C_IO_C 0xc5018 //
INTEL_I2C_IO_C
#define PCH_DISPLAY_A_PLL 0xc6014 //
INTEL_DISPLAY_A_PLL
@@ -242,6 +247,12 @@
#define PCH_DISPLAY_A_PLL_DIVISOR_1 0xc6044 //
INTEL_DISPLAY_A_PLL_DIVISOR_1
#define PCH_DISPLAY_B_PLL_DIVISOR_0 0xc6048 //
INTEL_DISPLAY_B_PLL_DIVISOR_0
#define PCH_DISPLAY_B_PLL_DIVISOR_1 0xc604c //
INTEL_DISPLAY_B_PLL_DIVISOR_1
+
+// South Display Engine (SDE) Transcoder and Port Controls
+#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 //
INTEL_DISPLAY_A_ANALOG_PORT
+#define PCH_DISPLAY_A_DIGITAL_PORT 0xe1120 //
INTEL_DISPLAY_A_DIGITAL_PORT
+#define PCH_DISPLAY_B_DIGITAL_PORT 0xe1140 //
INTEL_DISPLAY_B_DIGITAL_PORT
+#define PCH_DISPLAY_LVDS_PORT 0xe1180 //
INTEL_DISPLAY_LVDS_PORT
#define PCH_TRANSCODER_A_HTOTAL 0xe0000 //
INTEL_DISPLAY_A_HTOTAL
#define PCH_TRANSCODER_A_HBLANK 0xe0004 //
INTEL_DISPLAY_A_HBLANK
#define PCH_TRANSCODER_A_HSYNC 0xe0008 // INTEL_DISPLAY_A_HSYNC
@@ -254,12 +265,8 @@
#define PCH_TRANSCODER_B_VTOTAL 0xe100c //
INTEL_DISPLAY_B_VTOTAL
#define PCH_TRANSCODER_B_VBLANK 0xe1010 //
INTEL_DISPLAY_B_VBLANK
#define PCH_TRANSCODER_B_VSYNC 0xe1014 // INTEL_DISPLAY_B_VSYNC
-#define PCH_DISPLAY_A_PALETTE 0x4a000 //
INTEL_DISPLAY_A_PALETTE
-#define PCH_DISPLAY_B_PALETTE 0x4a800 //
INTEL_DISPLAY_B_PALETTE
#define PCH_LVDS_DETECTED (1 << 1)
-#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7)
-#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15)
// SandyBridge (SNB)
Other related posts:
- » [haiku-commits] r42852 - haiku/trunk/headers/private/graphics/intel_extreme - mmlr
