[haiku-commits] r42817 - haiku/trunk/src/add-ons/accelerants/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Mon, 10 Oct 2011 00:04:07 +0200 (CEST)
Author: kallisti5
Date: 2011-10-10 00:04:07 +0200 (Mon, 10 Oct 2011)
New Revision: 42817
Changeset: https://dev.haiku-os.org/changeset/42817
Modified:
haiku/trunk/src/add-ons/accelerants/radeon_hd/bios.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/display.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/display.h
haiku/trunk/src/add-ons/accelerants/radeon_hd/encoder.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
Log:
* remove some legacy code
* don't init asic unless needed
* do dpms by hand on mode set
* detect tv and skip during detection for now
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/bios.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/bios.cpp 2011-10-09
19:56:19 UTC (rev 42816)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/bios.cpp 2011-10-09
22:04:07 UTC (rev 42817)
@@ -159,13 +159,8 @@
radeon_bios_init_scratch();
atom_allocate_fb_scratch(gAtomContext);
- // TODO : Always post bios for now... not doing this
- // at a later date may save boot time
- atom_asic_init(gAtomContext);
-
- #if 0
// post card atombios if needed
- if (!radeon_bios_isposted()) {
+ if (radeon_bios_isposted() == false) {
TRACE("%s: init AtomBIOS for this card as it is not not
posted\n",
__func__);
// radeon_gpu_reset(); // <= r500 only?
@@ -174,7 +169,6 @@
TRACE("%s: AtomBIOS is already posted\n",
__func__);
}
- #endif
return B_OK;
}
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/display.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/display.cpp 2011-10-09
19:56:19 UTC (rev 42816)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/display.cpp 2011-10-09
22:04:07 UTC (rev 42817)
@@ -282,7 +282,6 @@
gConnector[i]->line_mux = ci.sucI2cId.ucAccess;
// TODO : give tv unique connector ids
- // TODO : ddc bus
// Always set CRT1 and CRT2 as VGA, some cards incorrectly set
// VGA ports as DVI
@@ -603,6 +602,15 @@
gConnector[connector_index]->type = connector_type;
gConnector[connector_index]->object_id
= connector_object_id;
+
+ if (connector_type == VIDEO_CONNECTOR_COMPOSITE
+ || connector_type == VIDEO_CONNECTOR_SVIDEO
+ || connector_type == VIDEO_CONNECTOR_9DIN) {
+ gConnector[connector_index]->encoder.is_tv =
true;
+ } else {
+ gConnector[connector_index]->encoder.is_tv =
false;
+ }
+
connector_index++;
}
} // end for each display path
@@ -624,6 +632,9 @@
for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) {
if (gConnector[id]->valid == false)
continue;
+ // TODO : currently we skip TV connectors during detection
+ if (gConnector[id]->encoder.is_tv == true)
+ continue;
if (displayIndex >= MAX_DISPLAY)
continue;
@@ -760,6 +771,7 @@
void
display_crtc_lock(uint8 crtc_id, int command)
{
+ TRACE("%s\n", __func__);
ENABLE_CRTC_PS_ALLOCATION args;
int index
= GetIndexIntoMasterTable(COMMAND,
UpdateCRTC_DoubleBufferRegisters);
@@ -776,8 +788,9 @@
void
display_crtc_blank(uint8 crtc_id, int command)
{
- int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
+ TRACE("%s\n", __func__);
BLANK_CRTC_PS_ALLOCATION args;
+ int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
memset(&args, 0, sizeof(args));
@@ -791,6 +804,7 @@
void
display_crtc_scale(uint8 crtc_id, display_mode *mode)
{
+ TRACE("%s\n", __func__);
ENABLE_SCALER_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
@@ -875,17 +889,19 @@
Write32(CRT, regs->grphYStart, 0);
Write32(CRT, regs->grphXEnd, mode->virtual_width);
Write32(CRT, regs->grphYEnd, mode->virtual_height);
- Write32(CRT, regs->grphPitch, bytesPerRow / 4);
+ Write32(CRT, regs->grphPitch, (bytesPerRow / 4));
Write32(CRT, regs->grphEnable, 1);
// Enable Frame buffer
Write32(CRT, regs->modeDesktopHeight, mode->virtual_height);
- Write32(CRT, regs->viewportStart, 0);
+ uint32 viewport_w = mode->timing.h_display;
+ uint32 viewport_h = (mode->timing.v_display + 1) & ~1;
+ Write32(CRT, regs->viewportStart, 0);
Write32(CRT, regs->viewportSize,
- mode->timing.v_display | (mode->timing.h_display << 16));
+ (viewport_w << 16) | viewport_h);
uint32 tmp = Read32(CRT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);
tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
@@ -893,91 +909,12 @@
Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);
// Pageflip to happen anywhere in vblank
-}
-
-void
-display_crtc_fb_set_legacy(uint8 crtc_id, display_mode *mode)
-{
- register_info* regs = gDisplay[crtc_id]->regs;
-
- uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int;
-
- Write32(CRT, regs->grphUpdate, (1<<16));
- // Lock for update (isn't this normally the other way around on
VGA?
-
- Write32Mask(CRT, regs->grphEnable, 1, 0x00000001);
- // Enable Frame buffer
-
- Write32(CRT, regs->grphControl, 0);
- // Reset stored depth, format, etc
-
- uint32 bytesPerPixel;
- uint32 bitsPerPixel;
-
- // set color mode on video card
- switch (mode->space) {
- case B_CMAP8:
- bytesPerPixel = 1;
- bitsPerPixel = 8;
- Write32Mask(CRT, regs->grphControl,
- 0, 0x00000703);
- break;
- case B_RGB15_LITTLE:
- bytesPerPixel = 2;
- bitsPerPixel = 15;
- Write32Mask(CRT, regs->grphControl,
- 0x000001, 0x00000703);
- break;
- case B_RGB16_LITTLE:
- bytesPerPixel = 2;
- bitsPerPixel = 16;
- Write32Mask(CRT, regs->grphControl,
- 0x000101, 0x00000703);
- break;
- case B_RGB24_LITTLE:
- bytesPerPixel = 4;
- bitsPerPixel = 24;
- Write32Mask(CRT, regs->grphControl,
- 0x000002, 0x00000703);
- break;
- case B_RGB32_LITTLE:
- default:
- bytesPerPixel = 4;
- bitsPerPixel = 32;
- Write32Mask(CRT, regs->grphControl,
- 0x000002, 0x00000703);
- break;
- }
-
- uint32 bytesPerRow = mode->virtual_width * bytesPerPixel;
-
- Write32(CRT, regs->grphSwapControl, 0);
- // only for chipsets > r600
-
- // Tell GPU which frame buffer address to draw from
- Write32(CRT, regs->grphPrimarySurfaceAddr, fbAddressInt & 0xFFFFFFFF);
- Write32(CRT, regs->grphSecondarySurfaceAddr, fbAddressInt & 0xFFFFFFFF);
-
- Write32(CRT, regs->grphSurfaceOffsetX, 0);
- Write32(CRT, regs->grphSurfaceOffsetY, 0);
- Write32(CRT, regs->grphXStart, 0);
- Write32(CRT, regs->grphYStart, 0);
- Write32(CRT, regs->grphXEnd, mode->virtual_width);
- Write32(CRT, regs->grphYEnd, mode->virtual_height);
- Write32(CRT, regs->grphPitch, bytesPerRow / 4);
-
- Write32(CRT, regs->modeDesktopHeight, mode->virtual_height);
-
- Write32(CRT, regs->grphUpdate, 0);
- // Unlock changed registers
-
// update shared info
gInfo->shared_info->bytes_per_row = bytesPerRow;
gInfo->shared_info->current_mode = *mode;
gInfo->shared_info->bits_per_pixel = bitsPerPixel;
- // TODO : recompute bandwidth via rv515_bandwidth_avivo_update
}
@@ -1078,6 +1015,7 @@
void
display_crtc_power(uint8 crtc_id, int command)
{
+ TRACE("%s\n", __func__);
int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
ENABLE_CRTC_PS_ALLOCATION args;
@@ -1093,6 +1031,7 @@
void
display_crtc_memreq(uint8 crtc_id, int command)
{
+ TRACE("%s\n", __func__);
int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
ENABLE_CRTC_PS_ALLOCATION args;
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/display.h
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/display.h 2011-10-09
19:56:19 UTC (rev 42816)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/display.h 2011-10-09
22:04:07 UTC (rev 42817)
@@ -69,7 +69,6 @@
void display_crtc_lock(uint8 crtc_id, int command);
void display_crtc_blank(uint8 crtc_id, int command);
void display_crtc_scale(uint8 crtc_id, display_mode *mode);
-void display_crtc_fb_set_legacy(uint8 crtc_id, display_mode *mode);
void display_crtc_fb_set_dce1(uint8 crtc_id, display_mode *mode);
void display_crtc_set(uint8 crtc_id, display_mode *mode);
void display_crtc_set_dtd(uint8 crtc_id, display_mode *mode);
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/encoder.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/encoder.cpp 2011-10-09
19:56:19 UTC (rev 42816)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/encoder.cpp 2011-10-09
22:04:07 UTC (rev 42817)
@@ -66,10 +66,10 @@
break;
case
ENCODER_OBJECT_ID_INTERNAL_LVDS:
case
ENCODER_OBJECT_ID_INTERNAL_LVTM1:
- //if
(radeon_encoder->devices
- // &
ATOM_DEVICE_LCD1_SUPPORT)
- //
args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
- //else
+ if
(gConnector[connector_index]->flags
+ &
ATOM_DEVICE_LCD1_SUPPORT)
+
args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
+ else
args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
break;
case
ENCODER_OBJECT_ID_INTERNAL_DVO1:
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-10-09
19:56:19 UTC (rev 42816)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-10-09
22:04:07 UTC (rev 42817)
@@ -102,23 +102,29 @@
{
switch(mode) {
case B_DPMS_ON:
+ TRACE("%s: ON\n", __func__);
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
continue;
+ display_crtc_lock(id, ATOM_ENABLE);
display_crtc_power(id, ATOM_ENABLE);
display_crtc_memreq(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_DISABLE);
+ display_crtc_lock(id, ATOM_DISABLE);
}
break;
case B_DPMS_STAND_BY:
case B_DPMS_SUSPEND:
case B_DPMS_OFF:
+ TRACE("%s: OFF\n", __func__);
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
continue;
+ display_crtc_lock(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_ENABLE);
display_crtc_memreq(id, ATOM_DISABLE);
display_crtc_power(id, ATOM_DISABLE);
+ display_crtc_lock(id, ATOM_DISABLE);
}
break;
}
@@ -129,8 +135,6 @@
radeon_set_display_mode(display_mode *mode)
{
// TODO : multi-monitor? for now we use VESA and not gDisplay edid
- radeon_dpms_set(B_DPMS_OFF);
-
// Set mode on each display
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
@@ -146,6 +150,9 @@
// *** CRT controler prep
display_crtc_lock(id, ATOM_ENABLE);
+ display_crtc_blank(id, ATOM_ENABLE);
+ display_crtc_memreq(id, ATOM_DISABLE);
+ display_crtc_power(id, ATOM_DISABLE);
// *** CRT controler mode set
// TODO : program SS
@@ -155,7 +162,6 @@
// TODO : vvvv : atombios_crtc_set_base
display_crtc_fb_set_dce1(id, mode);
- // display_crtc_fb_set_legacy(id, mode);
// atombios_overscan_setup
display_crtc_scale(id, mode);
@@ -163,6 +169,9 @@
encoder_mode_set(id, mode->timing.pixel_clock);
// *** CRT controler commit
+ display_crtc_blank(id, ATOM_DISABLE);
+ display_crtc_memreq(id, ATOM_ENABLE);
+ display_crtc_power(id, ATOM_ENABLE);
display_crtc_lock(id, ATOM_DISABLE);
// *** encoder commit
@@ -171,8 +180,6 @@
encoder_output_lock(false);
}
- radeon_dpms_set(B_DPMS_ON);
-
int32 crtstatus = Read32(CRT, D1CRTC_STATUS);
TRACE("CRT0 Status: 0x%X\n", crtstatus);
crtstatus = Read32(CRT, D2CRTC_STATUS);
Other related posts:
- » [haiku-commits] r42817 - haiku/trunk/src/add-ons/accelerants/radeon_hd - kallisti5
