[haiku-commits] r42509 - in haiku/trunk: headers/private/graphics/radeon_hd src/add-ons/accelerants/radeon_hd src/add-ons/kernel/drivers/graphics/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Fri, 29 Jul 2011 08:10:52 +0200 (CEST)
Author: kallisti5
Date: 2011-07-29 08:10:52 +0200 (Fri, 29 Jul 2011)
New Revision: 42509
Changeset: https://dev.haiku-os.org/changeset/42509
Modified:
haiku/trunk/headers/private/graphics/radeon_hd/radeon_hd.h
haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.h
haiku/trunk/src/add-ons/accelerants/radeon_hd/mc.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.h
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
Log:
* Little cleanup
* Add missing Idle call for connectors
* Reformulate blanking.. this should match what the
register is after the GTF vesa call
* Set FrameBuffer to card internal address
Modified: haiku/trunk/headers/private/graphics/radeon_hd/radeon_hd.h
===================================================================
--- haiku/trunk/headers/private/graphics/radeon_hd/radeon_hd.h 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/headers/private/graphics/radeon_hd/radeon_hd.h 2011-07-29
06:10:52 UTC (rev 42509)
@@ -83,6 +83,7 @@
addr_t frame_buffer_phys; // card PCI BAR
address of FB
area_id frame_buffer_area; // area of
memory mapped FB
+ uint32 frame_buffer_int; // card
internal FB location
uint32 frame_buffer_size; // card
internal FB aperture size
uint8* frame_buffer; // virtual
memory mapped FB
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.cpp 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.cpp 2011-07-29
06:10:52 UTC (rev 42509)
@@ -258,3 +258,10 @@
return B_OK;
}
+
+
+void
+LVDSAllIdle()
+{
+ LVDSPower(1, RHD_POWER_RESET);
+}
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.h
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.h 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/lvds.h 2011-07-29
06:10:52 UTC (rev 42509)
@@ -28,6 +28,7 @@
void LVDSVoltageControl(uint8 lvdsIndex);
void LVDSPower(uint8 lvdsIndex, int command);
status_t LVDSSet(uint8 lvdsIndex, display_mode *mode);
+void LVDSAllIdle();
#endif /* RADEON_HD_LVDS_H */
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/mc.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/mc.cpp 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/mc.cpp 2011-07-29
06:10:52 UTC (rev 42509)
@@ -65,9 +65,10 @@
return B_OK;
}
- if (oldFbLocation >> 32)
+ if (oldFbLocation >> 32) {
TRACE("%s: board claims to use a frame buffer address >
32-bits\n",
__func__);
+ }
uint32 idleState = MCIdle();
if (idleState > 0) {
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-07-29
06:10:52 UTC (rev 42509)
@@ -128,6 +128,7 @@
static void
CardBlankSet(uint8 crtid, bool blank)
{
+ return;
int blackColorReg
= crtid == 1 ? D2CRTC_BLACK_COLOR : D1CRTC_BLACK_COLOR;
int blankControlReg
@@ -149,34 +150,34 @@
get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel);
- #if 0
- // TMDSAllIdle // DVI / HDMI
- // LVTMAAllIdle // DVI
+ LVDSAllIdle();
+ // DVI / HDMI / LCD
+ TMDSAllIdle();
+ // DVI / HDMI
DACAllIdle();
+ // VGA
+ // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed
+ //uint64 fbAddress = gInfo->shared_info->frame_buffer_phys;
+ uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int;
+
// Set the inital frame buffer location in the memory controler
uint32 mcFbSize;
- MCFBLocation(0, &mcFbSize);
- MCFBSetup(Read32(OUT, R6XX_CONFIG_FB_BASE), mcFbSize);
- #endif
+ MCFBLocation(fbAddressInt, &mcFbSize);
+ //MCFBSetup(gInfo->shared_info->frame_buffer_int, mcFbSize);
Write32(CRT, regs->grphUpdate, (1<<16));
// Lock for update (isn't this normally the other way around on
VGA?
- // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed
- uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys;
-
// Tell GPU which frame buffer address to draw from
- Write32(CRT, regs->grphPrimarySurfaceAddr,
- fbAddress & 0xffffffff);
- Write32(CRT, regs->grphSecondarySurfaceAddr,
- fbAddress & 0xffffffff);
+ Write32(CRT, regs->grphPrimarySurfaceAddr, fbAddressInt & 0xffffffff);
+ Write32(CRT, regs->grphSecondarySurfaceAddr, fbAddressInt & 0xffffffff);
if (gInfo->shared_info->device_chipset >= (RADEON_R700 | 0x70)) {
Write32(CRT, regs->grphPrimarySurfaceAddrHigh,
- (fbAddress >> 32) & 0xf);
+ (fbAddressInt >> 32) & 0xf);
Write32(CRT, regs->grphSecondarySurfaceAddrHigh,
- (fbAddress >> 32) & 0xf);
+ (fbAddressInt >> 32) & 0xf);
}
Write32(CRT, regs->grphControl, 0);
@@ -248,10 +249,9 @@
displayTiming.h_total - 1);
// Blanking
- uint16 blankStart = MIN(displayTiming.h_sync_start,
- displayTiming.h_display);
- uint16 blankEnd = MAX(displayTiming.h_sync_end,
- displayTiming.h_total);
+ uint16 blankStart = displayTiming.h_total - displayTiming.h_sync_start;
+ uint16 blankEnd = displayTiming.h_total
+ + displayTiming.h_display - displayTiming.h_sync_start;
Write32(CRT, regs->crtHBlank,
blankStart | (blankEnd << 16));
@@ -267,10 +267,10 @@
Write32(CRT, regs->crtVTotal,
displayTiming.v_total - 1);
- blankStart = MIN(displayTiming.v_sync_start,
- displayTiming.v_display);
- blankEnd = MAX(displayTiming.v_sync_end,
- displayTiming.v_total);
+ // Blanking
+ blankStart = displayTiming.v_total - displayTiming.v_sync_start;
+ blankEnd = displayTiming.v_total
+ + displayTiming.v_display - displayTiming.v_sync_start;
Write32(CRT, regs->crtVBlank,
blankStart | (blankEnd << 16));
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.cpp 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.cpp 2011-07-29
06:10:52 UTC (rev 42509)
@@ -224,3 +224,10 @@
// TODO : HdmiSetMode(mode)
return B_OK;
}
+
+
+void
+TMDSAllIdle()
+{
+ TMDSPower(0, RHD_POWER_RESET);
+}
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.h
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.h 2011-07-29
03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/tmds.h 2011-07-29
06:10:52 UTC (rev 42509)
@@ -13,6 +13,7 @@
bool TMDSSense(uint8 tmdsIndex);
status_t TMDSPower(uint8 tmdsIndex, int command);
status_t TMDSSet(uint8 tmdsIndex, display_mode *mode);
+void TMDSAllIdle();
#endif
Modified:
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
===================================================================
--- haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
2011-07-29 03:32:01 UTC (rev 42508)
+++ haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
2011-07-29 06:10:52 UTC (rev 42509)
@@ -99,6 +99,8 @@
info.shared_info->frame_buffer_area = info.framebuffer_area;
info.shared_info->frame_buffer_phys
= info.pci->u.h0.base_registers[RHD_FB_BAR];
+ info.shared_info->frame_buffer_int
+ = read32(info.registers + R6XX_CONFIG_FB_BASE);
// Pull active monitor VESA EDID from boot loader
edid1_info* edidInfo = (edid1_info*)get_boot_item(EDID_BOOT_INFO,
Other related posts:
- » [haiku-commits] r42509 - in haiku/trunk: headers/private/graphics/radeon_hd src/add-ons/accelerants/radeon_hd src/add-ons/kernel/drivers/graphics/radeon_hd - kallisti5
