[haiku-commits] r42411 - haiku/trunk/src/add-ons/accelerants/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Mon, 11 Jul 2011 20:46:37 +0200 (CEST)
Author: kallisti5
Date: 2011-07-11 20:46:37 +0200 (Mon, 11 Jul 2011)
New Revision: 42411
Changeset: https://dev.haiku-os.org/changeset/42411
Modified:
haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/dac.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/pll.cpp
Log:
* remove superfluous parentheses as per Axel
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
2011-07-11 18:05:46 UTC (rev 42410)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
2011-07-11 18:46:37 UTC (rev 42411)
@@ -247,52 +247,52 @@
// r600 - r700 are D1 or D2 based on primary / secondary crt
gRegister->vgaControl
- = (crtid == 1) ? D2VGA_CONTROL : D1VGA_CONTROL;
+ = crtid == 1 ? D2VGA_CONTROL : D1VGA_CONTROL;
gRegister->grphEnable
- = (crtid == 1) ? D2GRPH_ENABLE : D1GRPH_ENABLE;
+ = crtid == 1 ? D2GRPH_ENABLE : D1GRPH_ENABLE;
gRegister->grphControl
- = (crtid == 1) ? D2GRPH_CONTROL : D1GRPH_CONTROL;
+ = crtid == 1 ? D2GRPH_CONTROL : D1GRPH_CONTROL;
gRegister->grphSwapControl
- = (crtid == 1) ? D2GRPH_SWAP_CNTL : D1GRPH_SWAP_CNTL;
+ = crtid == 1 ? D2GRPH_SWAP_CNTL : D1GRPH_SWAP_CNTL;
gRegister->grphPrimarySurfaceAddr
- = (crtid == 1) ? D2GRPH_PRIMARY_SURFACE_ADDRESS
+ = crtid == 1 ? D2GRPH_PRIMARY_SURFACE_ADDRESS
: D1GRPH_PRIMARY_SURFACE_ADDRESS;
gRegister->grphSecondarySurfaceAddr
- = (crtid == 1) ? D2GRPH_SECONDARY_SURFACE_ADDRESS
+ = crtid == 1 ? D2GRPH_SECONDARY_SURFACE_ADDRESS
: D1GRPH_SECONDARY_SURFACE_ADDRESS;
// Surface Address high only used on r770+
gRegister->grphPrimarySurfaceAddrHigh
- = (crtid == 1) ?
R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ = crtid == 1 ? R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
: R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
gRegister->grphSecondarySurfaceAddrHigh
- = (crtid == 1) ?
R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ = crtid == 1 ?
R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
: R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
gRegister->grphPitch
- = (crtid == 1) ? D2GRPH_PITCH : D1GRPH_PITCH;
+ = crtid == 1 ? D2GRPH_PITCH : D1GRPH_PITCH;
gRegister->grphSurfaceOffsetX
- = (crtid == 1) ? D2GRPH_SURFACE_OFFSET_X :
D1GRPH_SURFACE_OFFSET_X;
+ = crtid == 1 ? D2GRPH_SURFACE_OFFSET_X :
D1GRPH_SURFACE_OFFSET_X;
gRegister->grphSurfaceOffsetY
- = (crtid == 1) ? D2GRPH_SURFACE_OFFSET_Y :
D1GRPH_SURFACE_OFFSET_Y;
+ = crtid == 1 ? D2GRPH_SURFACE_OFFSET_Y :
D1GRPH_SURFACE_OFFSET_Y;
gRegister->grphXStart
- = (crtid == 1) ? D2GRPH_X_START : D1GRPH_X_START;
+ = crtid == 1 ? D2GRPH_X_START : D1GRPH_X_START;
gRegister->grphYStart
- = (crtid == 1) ? D2GRPH_Y_START : D1GRPH_Y_START;
+ = crtid == 1 ? D2GRPH_Y_START : D1GRPH_Y_START;
gRegister->grphXEnd
- = (crtid == 1) ? D2GRPH_X_END : D1GRPH_X_END;
+ = crtid == 1 ? D2GRPH_X_END : D1GRPH_X_END;
gRegister->grphYEnd
- = (crtid == 1) ? D2GRPH_Y_END : D1GRPH_Y_END;
+ = crtid == 1 ? D2GRPH_Y_END : D1GRPH_Y_END;
gRegister->crtControl
- = (crtid == 1) ? D2CRTC_CONTROL : D1CRTC_CONTROL;
+ = crtid == 1 ? D2CRTC_CONTROL : D1CRTC_CONTROL;
gRegister->modeDesktopHeight
- = (crtid == 1) ? D2MODE_DESKTOP_HEIGHT :
D1MODE_DESKTOP_HEIGHT;
+ = crtid == 1 ? D2MODE_DESKTOP_HEIGHT :
D1MODE_DESKTOP_HEIGHT;
gRegister->modeDataFormat
- = (crtid == 1) ? D2MODE_DATA_FORMAT :
D1MODE_DATA_FORMAT;
+ = crtid == 1 ? D2MODE_DATA_FORMAT : D1MODE_DATA_FORMAT;
gRegister->viewportStart
- = (crtid == 1) ? D2MODE_VIEWPORT_START :
D1MODE_VIEWPORT_START;
+ = crtid == 1 ? D2MODE_VIEWPORT_START :
D1MODE_VIEWPORT_START;
gRegister->viewportSize
- = (crtid == 1) ? D2MODE_VIEWPORT_SIZE :
D1MODE_VIEWPORT_SIZE;
+ = crtid == 1 ? D2MODE_VIEWPORT_SIZE :
D1MODE_VIEWPORT_SIZE;
} else {
// this really shouldn't happen unless a driver PCIID chipset
is wrong
TRACE("%s, unknown Radeon chipset: r%X\n", __func__,
@@ -305,35 +305,35 @@
gRegister->crtid = crtid;
gRegister->modeCenter
- = (crtid == 1) ? D2MODE_CENTER : D1MODE_CENTER;
+ = crtid == 1 ? D2MODE_CENTER : D1MODE_CENTER;
gRegister->grphUpdate
- = (crtid == 1) ? D2GRPH_UPDATE : D1GRPH_UPDATE;
+ = crtid == 1 ? D2GRPH_UPDATE : D1GRPH_UPDATE;
gRegister->crtHPolarity
- = (crtid == 1) ? D2CRTC_H_SYNC_A_CNTL : D1CRTC_H_SYNC_A_CNTL;
+ = crtid == 1 ? D2CRTC_H_SYNC_A_CNTL : D1CRTC_H_SYNC_A_CNTL;
gRegister->crtVPolarity
- = (crtid == 1) ? D2CRTC_V_SYNC_A_CNTL : D1CRTC_V_SYNC_A_CNTL;
+ = crtid == 1 ? D2CRTC_V_SYNC_A_CNTL : D1CRTC_V_SYNC_A_CNTL;
gRegister->crtHTotal
- = (crtid == 1) ? D2CRTC_H_TOTAL : D1CRTC_H_TOTAL;
+ = crtid == 1 ? D2CRTC_H_TOTAL : D1CRTC_H_TOTAL;
gRegister->crtVTotal
- = (crtid == 1) ? D2CRTC_V_TOTAL : D1CRTC_V_TOTAL;
+ = crtid == 1 ? D2CRTC_V_TOTAL : D1CRTC_V_TOTAL;
gRegister->crtHSync
- = (crtid == 1) ? D2CRTC_H_SYNC_A : D1CRTC_H_SYNC_A;
+ = crtid == 1 ? D2CRTC_H_SYNC_A : D1CRTC_H_SYNC_A;
gRegister->crtVSync
- = (crtid == 1) ? D2CRTC_V_SYNC_A : D1CRTC_V_SYNC_A;
+ = crtid == 1 ? D2CRTC_V_SYNC_A : D1CRTC_V_SYNC_A;
gRegister->crtHBlank
- = (crtid == 1) ? D2CRTC_H_BLANK_START_END :
D1CRTC_H_BLANK_START_END;
+ = crtid == 1 ? D2CRTC_H_BLANK_START_END :
D1CRTC_H_BLANK_START_END;
gRegister->crtVBlank
- = (crtid == 1) ? D2CRTC_V_BLANK_START_END :
D1CRTC_V_BLANK_START_END;
+ = crtid == 1 ? D2CRTC_V_BLANK_START_END :
D1CRTC_V_BLANK_START_END;
gRegister->crtInterlace
- = (crtid == 1) ? D2CRTC_INTERLACE_CONTROL :
D1CRTC_INTERLACE_CONTROL;
+ = crtid == 1 ? D2CRTC_INTERLACE_CONTROL :
D1CRTC_INTERLACE_CONTROL;
gRegister->crtCountControl
- = (crtid == 1) ? D2CRTC_COUNT_CONTROL : D1CRTC_COUNT_CONTROL;
+ = crtid == 1 ? D2CRTC_COUNT_CONTROL : D1CRTC_COUNT_CONTROL;
gRegister->sclUpdate
- = (crtid == 1) ? D2SCL_UPDATE : D1SCL_UPDATE;
+ = crtid == 1 ? D2SCL_UPDATE : D1SCL_UPDATE;
gRegister->sclEnable
- = (crtid == 1) ? D2SCL_ENABLE : D1SCL_ENABLE;
+ = crtid == 1 ? D2SCL_ENABLE : D1SCL_ENABLE;
gRegister->sclTapControl
- = (crtid == 1) ? D2SCL_TAP_CONTROL : D1SCL_TAP_CONTROL;
+ = crtid == 1 ? D2SCL_TAP_CONTROL : D1SCL_TAP_CONTROL;
TRACE("%s, registers for ATI chipset r%X crt #%d loaded\n", __func__,
info.device_chipset, crtid);
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/dac.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/dac.cpp 2011-07-11
18:05:46 UTC (rev 42410)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/dac.cpp 2011-07-11
18:46:37 UTC (rev 42411)
@@ -25,7 +25,7 @@
bool
DACSense(uint8 dacIndex)
{
- uint32 dacOffset = (dacIndex == 1) ? REG_DACB_OFFSET : REG_DACA_OFFSET;
+ uint32 dacOffset = dacIndex == 1 ? REG_DACB_OFFSET : REG_DACA_OFFSET;
// Backup current DAC values
uint32 compEnable = Read32(OUT, dacOffset + DACA_COMPARATOR_ENABLE);
@@ -183,7 +183,7 @@
if (whiteFine)
mask |= 0xFF << 8;
- uint32 dacOffset = (dacIndex == 1) ? RV620_REG_DACA_OFFSET
+ uint32 dacOffset = dacIndex == 1 ? RV620_REG_DACA_OFFSET
: RV620_REG_DACB_OFFSET;
Write32Mask(OUT, dacOffset + RV620_DACA_MACRO_CNTL, mode, 0xFF);
@@ -203,7 +203,7 @@
// reset the FMT register
// TODO : ah-la external DxFMTSet
- uint32 fmtOffset = (crtid == 0) ? FMT1_REG_OFFSET : FMT2_REG_OFFSET;
+ uint32 fmtOffset = crtid == 0 ? FMT1_REG_OFFSET : FMT2_REG_OFFSET;
Write32(OUT, fmtOffset + RV620_FMT1_BIT_DEPTH_CONTROL, 0);
Write32Mask(OUT, fmtOffset + RV620_FMT1_CONTROL, 0,
@@ -234,7 +234,7 @@
if (whiteFine)
mask |= 0xFF << 8;
- uint32 dacOffset = (dacIndex == 1) ? REG_DACB_OFFSET : REG_DACA_OFFSET;
+ uint32 dacOffset = dacIndex == 1 ? REG_DACB_OFFSET : REG_DACA_OFFSET;
Write32Mask(OUT, dacOffset + DACA_CONTROL1, standard, 0x000000FF);
/* white level fine adjust */
@@ -286,7 +286,7 @@
{
TRACE("%s: dacIndex: %d; mode: %d\n", __func__, dacIndex, mode);
- uint32 dacOffset = (dacIndex == 1) ? RV620_REG_DACB_OFFSET
+ uint32 dacOffset = dacIndex == 1 ? RV620_REG_DACB_OFFSET
: RV620_REG_DACA_OFFSET;
uint32 powerdown;
@@ -328,7 +328,7 @@
void
DACPowerLegacy(uint8 dacIndex, int mode)
{
- uint32 dacOffset = (dacIndex == 1) ? REG_DACB_OFFSET : REG_DACA_OFFSET;
+ uint32 dacOffset = dacIndex == 1 ? REG_DACB_OFFSET : REG_DACA_OFFSET;
uint32 powerdown;
switch (mode) {
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-07-11
18:05:46 UTC (rev 42410)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-07-11
18:46:37 UTC (rev 42411)
@@ -131,9 +131,9 @@
CardBlankSet(uint8 crtid, bool blank)
{
int blackColorReg
- = (crtid == 1) ? D2CRTC_BLACK_COLOR : D1CRTC_BLACK_COLOR;
+ = crtid == 1 ? D2CRTC_BLACK_COLOR : D1CRTC_BLACK_COLOR;
int blankControlReg
- = (crtid == 1) ? D2CRTC_BLANK_CONTROL : D1CRTC_BLANK_CONTROL;
+ = crtid == 1 ? D2CRTC_BLANK_CONTROL : D1CRTC_BLANK_CONTROL;
Write32(CRT, blackColorReg, 0);
Write32Mask(CRT, blankControlReg, blank ? 1 << 8 : 0, 1 << 8);
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/pll.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/pll.cpp 2011-07-11
18:05:46 UTC (rev 42410)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/pll.cpp 2011-07-11
18:46:37 UTC (rev 42411)
@@ -133,7 +133,7 @@
status_t
PLLPower(uint8 pllIndex, int command)
{
- uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
+ uint16 pllControlReg = pllIndex == 1 ? P2PLL_CNTL : P1PLL_CNTL;
bool hasDccg = DCCGCLKAvailable(pllIndex);
@@ -188,10 +188,10 @@
if (info.device_chipset >= (RADEON_R600 | 0x20)) {
uint16 pllDiffPostReg
- = (pllIndex == 1) ?
RV620_EXT2_DIFF_POST_DIV_CNTL
+ = pllIndex == 1 ?
RV620_EXT2_DIFF_POST_DIV_CNTL
: RV620_EXT1_DIFF_POST_DIV_CNTL;
uint16 pllDiffDriverEnable
- = (pllIndex == 1) ?
(uint16)RV62_EXT2_DIFF_DRIVER_ENABLE
+ = pllIndex == 1 ?
(uint16)RV62_EXT2_DIFF_DRIVER_ENABLE
:
(uint16)RV62_EXT1_DIFF_DRIVER_ENABLE;
// Sometimes we have to keep an unused PLL
running. X Bug #18016
@@ -255,27 +255,27 @@
uint32 referenceTemp = reference;
/* Internal PLL Registers */
- uint16 pllCntl = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
+ uint16 pllCntl = pllIndex == 1 ? P2PLL_CNTL : P1PLL_CNTL;
uint16 pllIntSSCntl
- = (pllIndex == 1) ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
+ = pllIndex == 1 ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
/* External PLL Registers */
uint16 pllExtCntl
- = (pllIndex == 1) ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
+ = pllIndex == 1 ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
uint16 pllExtUpdateCntl
- = (pllIndex == 1) ? EXT2_PPLL_UPDATE_CNTL :
EXT1_PPLL_UPDATE_CNTL;
+ = pllIndex == 1 ? EXT2_PPLL_UPDATE_CNTL : EXT1_PPLL_UPDATE_CNTL;
uint16 pllExtUpdateLock
- = (pllIndex == 1) ? EXT2_PPLL_UPDATE_LOCK :
EXT1_PPLL_UPDATE_LOCK;
+ = pllIndex == 1 ? EXT2_PPLL_UPDATE_LOCK : EXT1_PPLL_UPDATE_LOCK;
uint16 pllExtPostDiv
- = (pllIndex == 1) ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
uint16 pllExtPostDivSrc
- = (pllIndex == 1) ? EXT2_PPLL_POST_DIV_SRC :
EXT1_PPLL_POST_DIV_SRC;
+ = pllIndex == 1 ? EXT2_PPLL_POST_DIV_SRC :
EXT1_PPLL_POST_DIV_SRC;
uint16 pllExtFeedbackDiv
- = (pllIndex == 1) ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
uint16 pllExtRefDiv
- = (pllIndex == 1) ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
uint16 pllExtRefDivSrc
- = (pllIndex == 1) ? EXT2_PPLL_REF_DIV_SRC :
EXT1_PPLL_REF_DIV_SRC;
+ = pllIndex == 1 ? EXT2_PPLL_REF_DIV_SRC : EXT1_PPLL_REF_DIV_SRC;
radeon_shared_info &info = *gInfo->shared_info;
@@ -364,31 +364,31 @@
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RESET);
/* Internal PLL Registers */
- uint16 pllCntl = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
+ uint16 pllCntl = pllIndex == 1 ? P2PLL_CNTL : P1PLL_CNTL;
uint16 pllIntSSCntl
- = (pllIndex == 1) ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
+ = pllIndex == 1 ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
/* External PLL Registers */
uint16 pllExtCntl
- = (pllIndex == 1) ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
+ = pllIndex == 1 ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
//uint16 pllExtUpdateCntl
- // = (pllIndex == 1) ? EXT2_PPLL_UPDATE_CNTL :
EXT1_PPLL_UPDATE_CNTL;
+ // = pllIndex == 1 ? EXT2_PPLL_UPDATE_CNTL : EXT1_PPLL_UPDATE_CNTL;
uint16 pllExtUpdateLock
- = (pllIndex == 1) ? EXT2_PPLL_UPDATE_LOCK :
EXT1_PPLL_UPDATE_LOCK;
+ = pllIndex == 1 ? EXT2_PPLL_UPDATE_LOCK : EXT1_PPLL_UPDATE_LOCK;
uint16 pllExtPostDiv
- = (pllIndex == 1) ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
uint16 pllExtPostDivSrc
- = (pllIndex == 1) ? EXT2_PPLL_POST_DIV_SRC :
EXT1_PPLL_POST_DIV_SRC;
+ = pllIndex == 1 ? EXT2_PPLL_POST_DIV_SRC :
EXT1_PPLL_POST_DIV_SRC;
uint16 pllExtPostDivSym
- = (pllIndex == 1) ? EXT2_SYM_PPLL_POST_DIV :
EXT1_SYM_PPLL_POST_DIV;
+ = pllIndex == 1 ? EXT2_SYM_PPLL_POST_DIV :
EXT1_SYM_PPLL_POST_DIV;
uint16 pllExtFeedbackDiv
- = (pllIndex == 1) ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
uint16 pllExtRefDiv
- = (pllIndex == 1) ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
+ = pllIndex == 1 ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
//uint16 pllExtRefDivSrc
- // = (pllIndex == 1) ? EXT2_PPLL_REF_DIV_SRC :
EXT1_PPLL_REF_DIV_SRC;
+ // = pllIndex == 1 ? EXT2_PPLL_REF_DIV_SRC : EXT1_PPLL_REF_DIV_SRC;
uint16 pllExtDispClkCntl
- = (pllIndex == 1) ? P2PLL_DISP_CLK_CNTL : P1PLL_DISP_CLK_CNTL;
+ = pllIndex == 1 ? P2PLL_DISP_CLK_CNTL : P1PLL_DISP_CLK_CNTL;
Write32Mask(PLL, pllIntSSCntl, 0, 0x00000001);
// Disable Spread Spectrum
@@ -474,7 +474,7 @@
status_t
PLLCalibrate(uint8 pllIndex)
{
- uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
+ uint16 pllControlReg = pllIndex == 1 ? P2PLL_CNTL : P1PLL_CNTL;
Write32Mask(PLL, pllControlReg, 1, 0x01);
// PLL Reset
@@ -513,12 +513,12 @@
if (crtid == 0) {
pll2IsCurrent = Read32(PLL, PCLK_CRTC1_CNTL) & 0x00010000;
- Write32Mask(PLL, PCLK_CRTC1_CNTL, (pllIndex == 0) ? 0x00010000
: 0,
+ Write32Mask(PLL, PCLK_CRTC1_CNTL, pllIndex == 0 ? 0x00010000 :
0,
0x00010000);
} else {
pll2IsCurrent = Read32(PLL, PCLK_CRTC2_CNTL) & 0x00010000;
- Write32Mask(PLL, PCLK_CRTC2_CNTL, (pllIndex == 0) ? 0x00010000
: 0,
+ Write32Mask(PLL, PCLK_CRTC2_CNTL, pllIndex == 0 ? 0x00010000 :
0,
0x00010000);
}
Other related posts:
- » [haiku-commits] r42411 - haiku/trunk/src/add-ons/accelerants/radeon_hd - kallisti5
