[haiku-commits] r38944 - haiku/trunk/src/system/boot/platform/amiga_m68k
- From: revol@xxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Sun, 10 Oct 2010 22:44:33 +0200 (CEST)
Author: mmu_man
Date: 2010-10-10 22:44:33 +0200 (Sun, 10 Oct 2010)
New Revision: 38944
Changeset: http://dev.haiku-os.org/changeset/38944
Added:
haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.h
Removed:
haiku/trunk/src/system/boot/platform/amiga_m68k/amicalls.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/amicalls.h
Modified:
haiku/trunk/src/system/boot/platform/amiga_m68k/Handle.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/Jamfile
haiku/trunk/src/system/boot/platform/amiga_m68k/console.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/cpu.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/debug.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/devices.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/keyboard.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/mmu.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/shell.S
haiku/trunk/src/system/boot/platform/amiga_m68k/start.cpp
haiku/trunk/src/system/boot/platform/amiga_m68k/video.cpp
Log:
s/amicalls/rom_calls/
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/Handle.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/Handle.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/Handle.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -9,7 +9,7 @@
#include <util/kernel_cpp.h>
#include "Handle.h"
-#include "amicalls.h"
+#include "rom_calls.h"
/*
* (X)BIOS supports char and block devices with a separate namespace
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/Jamfile
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/Jamfile 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/Jamfile 2010-10-10
20:44:33 UTC (rev 38944)
@@ -29,7 +29,7 @@
KernelMergeObject boot_platform_amiga_m68k_other.o :
# shell.S
start.cpp
- amicalls.cpp
+ rom_calls.cpp
debug.cpp
#bios.S
console.cpp
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/console.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/console.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/console.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -8,7 +8,7 @@
#include <SupportDefs.h>
#include <string.h>
-#include "amicalls.h"
+#include "rom_calls.h"
#include <util/kernel_cpp.h>
#include "Handle.h"
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/cpu.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/cpu.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/cpu.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -8,7 +8,7 @@
#include "cpu.h"
-#include "amicalls.h"
+#include "rom_calls.h"
#include <OS.h>
#include <boot/platform.h>
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/debug.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/debug.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/debug.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -5,7 +5,7 @@
#include "keyboard.h"
-#include "amicalls.h"
+#include "rom_calls.h"
#include <boot/platform.h>
#include <boot/stdio.h>
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/devices.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/devices.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/devices.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -13,7 +13,7 @@
#include <string.h>
#include "Handle.h"
-#include "amicalls.h"
+#include "rom_calls.h"
//#define TRACE_DEVICES
#ifdef TRACE_DEVICES
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/keyboard.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/keyboard.cpp
2010-10-10 20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/keyboard.cpp
2010-10-10 20:44:33 UTC (rev 38944)
@@ -5,7 +5,7 @@
#include "keyboard.h"
-#include "amicalls.h"
+#include "rom_calls.h"
#include <boot/platform.h>
Modified: haiku/trunk/src/system/boot/platform/amiga_m68k/mmu.cpp
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/mmu.cpp 2010-10-10
20:41:41 UTC (rev 38943)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/mmu.cpp 2010-10-10
20:44:33 UTC (rev 38944)
@@ -7,7 +7,7 @@
#include "amiga_memory_map.h"
-#include "amicalls.h"
+#include "rom_calls.h"
#include "mmu.h"
#include <boot/platform.h>
Copied: haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.cpp (from rev
38942, haiku/trunk/src/system/boot/platform/amiga_m68k/amicalls.cpp)
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.cpp
(rev 0)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.cpp
2010-10-10 20:44:33 UTC (rev 38944)
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2010, François Revol, revol@xxxxxxxx All rights reserved.
+ * Distributed under the terms of the MIT License.
+ */
+
+
+#include <boot/platform.h>
+#include <boot/stage2.h>
+#include <boot/stdio.h>
+#include <stdarg.h>
+
+#include <Errors.h>
+
+#include "rom_calls.h"
+
+
+
+/*! Maps Amiga error codes to native errors
+ */
+extern "C" status_t
+exec_error(int32 err)
+{
+ switch (err) {
+ case IOERR_OPENFAIL:
+ return B_DEV_BAD_DRIVE_NUM;
+ case IOERR_ABORTED:
+ return B_INTERRUPTED;
+ case IOERR_NOCMD:
+ return B_BAD_VALUE;
+ case IOERR_BADLENGTH:
+ return B_BAD_VALUE;
+ case IOERR_BADADDRESS:
+ return B_BAD_ADDRESS;
+ case IOERR_UNITBUSY:
+ return B_DEV_NOT_READY;
+ case IOERR_SELFTEST:
+ return B_NOT_INITIALIZED;
+ default:
+ return B_ERROR;
+ }
+}
+
+
Copied: haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.h (from rev
38943, haiku/trunk/src/system/boot/platform/amiga_m68k/amicalls.h)
===================================================================
--- haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.h
(rev 0)
+++ haiku/trunk/src/system/boot/platform/amiga_m68k/rom_calls.h 2010-10-10
20:44:33 UTC (rev 38944)
@@ -0,0 +1,1105 @@
+/*
+ * Copyright 2010, Haiku, Inc. All Rights Reserved.
+ * Distributed under the terms of the MIT license.
+ *
+ * Author:
+ * François Revol, revol@xxxxxxxx
+ *
+ */
+#ifndef _AMICALLS_H
+#define _AMICALLS_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __ASSEMBLER__
+#include <OS.h>
+#include <SupportDefs.h>
+
+/*
+ General macros for Amiga function calls. Not all the possibilities have
+ been created - only the ones which exist in OS 3.1. Third party libraries
+ and future versions of AmigaOS will maybe need some new ones...
+
+ LPX - functions that take X arguments.
+
+ Modifiers (variations are possible):
+ NR - no return (void),
+ A4, A5 - "a4" or "a5" is used as one of the arguments,
+ UB - base will be given explicitly by user (see cia.resource).
+ FP - one of the parameters has type "pointer to function".
+
+ "bt" arguments are not used - they are provided for backward compatibility
+ only.
+*/
+/* those were taken from fd2pragma, but no copyright seems to be claimed on
them */
+
+#define LP0(offs, rt, name, bt, bn) \
+({ \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP0NR(offs, name, bt, bn) \
+({ \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP1NR(offs, name, t1, v1, r1, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only graphics.library/AttemptLockLayerRom() */
+#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom()
*/
+#define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only exec.library/Supervisor() */
+#define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ __asm volatile ("exg d7,a5\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a5" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only cia.resource/AbleICR() and cia.resource/SetICR() */
+#define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r"(_n1), "rf"(_n2) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Only dos.library/InternalUnLoadSeg() */
+#define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only cia.resource/AddICRVector() */
+#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Only cia.resource/RemICRVector() */
+#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only exec.library/SetFunction() */
+#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt)
\
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Only graphics.library/SetCollision() */
+#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt,
bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only exec.library/RawDoFmt() */
+#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
bt, bn, fpt) \
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5,
v5, r5, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only exec.library/MakeLibrary() */
+#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, bt, bn, fpt) \
+({ \
+ typedef fpt; \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Only reqtools.library/XXX() */
+#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ __asm volatile ("exg d7,a4\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a4" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, t6, v6, r6, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5,
v5, r5, t6, v6, r6, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5,
v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* Only workbench.library/AddAppIconA() */
+#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ __asm volatile ("exg d7,a4\n\tjsr %%a6@(-"#offs":W)\n\texg d7,a4" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* Would you believe that there really are beasts that need more than 7
+ arguments? :-) */
+
+/* For example intuition.library/AutoRequest() */
+#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ t8 _##name##_v8 = (v8); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ register t8 _n8 __asm(#r8) = _##name##_v8; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* For example intuition.library/ModifyProp() */
+#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5,
v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ t8 _##name##_v8 = (v8); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ register t8 _n8 __asm(#r8) = _##name##_v8; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
+})
+
+/* For example layers.library/CreateUpfrontHookLayer() */
+#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4,
t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ t8 _##name##_v8 = (v8); \
+ t9 _##name##_v9 = (v9); \
+ ({ \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register rt _##name##_re __asm("d0"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ register t8 _n8 __asm(#r8) = _##name##_v8; \
+ register t9 _n9 __asm(#r9) = _##name##_v9; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
+ : "fp0", "fp1", "cc", "memory"); \
+ _##name##_re; \
+ }); \
+})
+
+/* For example intuition.library/NewModifyProp() */
+#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5,
v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
+({ \
+ t1 _##name##_v1 = (v1); \
+ t2 _##name##_v2 = (v2); \
+ t3 _##name##_v3 = (v3); \
+ t4 _##name##_v4 = (v4); \
+ t5 _##name##_v5 = (v5); \
+ t6 _##name##_v6 = (v6); \
+ t7 _##name##_v7 = (v7); \
+ t8 _##name##_v8 = (v8); \
+ t9 _##name##_v9 = (v9); \
+ { \
+ register int _d0 __asm("d0"); \
+ register int _d1 __asm("d1"); \
+ register int _a0 __asm("a0"); \
+ register int _a1 __asm("a1"); \
+ register void *const _##name##_bn __asm("a6") = (bn); \
+ register t1 _n1 __asm(#r1) = _##name##_v1; \
+ register t2 _n2 __asm(#r2) = _##name##_v2; \
+ register t3 _n3 __asm(#r3) = _##name##_v3; \
+ register t4 _n4 __asm(#r4) = _##name##_v4; \
+ register t5 _n5 __asm(#r5) = _##name##_v5; \
+ register t6 _n6 __asm(#r6) = _##name##_v6; \
+ register t7 _n7 __asm(#r7) = _##name##_v7; \
+ register t8 _n8 __asm(#r8) = _##name##_v8; \
+ register t9 _n9 __asm(#r9) = _##name##_v9; \
+ __asm volatile ("jsr %%a6@(-"#offs":W)" \
+ : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
+ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4),
"rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
+ : "fp0", "fp1", "cc", "memory"); \
+ } \
[... truncated: 314 lines follow ...]
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