hrev56197 adds 1 changeset to branch 'master'
old head: ea56f5e0bec93718119b8cb40a0dec69831f7723
new head: 774c33c2a7010dc5bfa180c45a68040640142a03
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=774c33c2a701+%5Eea56f5e0bec9
----------------------------------------------------------------------------
774c33c2a701: radeon_hd: Drop unused overlay, cursor registers
* Also drop unused vblank semaphore storage
* Spotted by X512. These are from intel_extreme
which was used as a base *ages* ago.
Change-Id: I2a6baaa4849baeb8c8cf10e2046d0fbe10c3a356
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5389
Reviewed-by: Alex von Gluck IV <kallisti5@xxxxxxxxxxx>
Reviewed-by: waddlesplash <waddlesplash@xxxxxxxxx>
Tested-by: Commit checker robot <no-reply+buildbot@xxxxxxxxxxxx>
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev56197
Commit: 774c33c2a7010dc5bfa180c45a68040640142a03
URL: https://git.haiku-os.org/haiku/commit/?id=774c33c2a701
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Sun Jun 19 17:00:14 2022 UTC
Committer: waddlesplash <waddlesplash@xxxxxxxxx>
Commit-Date: Mon Jun 20 02:46:55 2022 UTC
----------------------------------------------------------------------------
1 file changed, 1 insertion(+), 216 deletions(-)
headers/private/graphics/radeon_hd/radeon_hd.h | 217 +--------------------
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diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h
b/headers/private/graphics/radeon_hd/radeon_hd.h
index 8584278be6..eed8d1107b 100644
--- a/headers/private/graphics/radeon_hd/radeon_hd.h
+++ b/headers/private/graphics/radeon_hd/radeon_hd.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
+ * Copyright 2006-2022, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
@@ -206,9 +206,6 @@ struct ring_buffer {
};
-struct overlay_registers;
-
-
struct radeon_shared_info {
uint32 deviceIndex; // accelerant index
uint32 pciID; // device pci id
@@ -245,23 +242,6 @@ struct radeon_shared_info {
ring_buffer primary_ring_buffer;
- int32 overlay_channel_used;
- bool overlay_active;
- uint32 overlay_token;
- addr_t physical_overlay_registers;
- uint32 overlay_offset;
-
- bool hardware_cursor_enabled;
- sem_id vblank_sem;
-
- uint8* cursor_memory;
- addr_t physical_cursor_memory;
- uint32 cursor_buffer_offset;
- uint32 cursor_format;
- bool cursor_visible;
- uint16 cursor_hot_x;
- uint16 cursor_hot_y;
-
char deviceName[MAX_NAME_LENGTH];
uint16 chipsetID;
char chipsetName[MAX_NAME_LENGTH];
@@ -312,200 +292,5 @@ struct radeon_free_graphics_memory {
#define OLD_CONFIG_APER_SIZE 0x0108 // <r600
#define CONFIG_MEMSIZE 0x5428 // r600>
-// PCI bridge memory management
-
-// overlay
-
-#define RADEON_OVERLAY_UPDATE 0x30000
-#define RADEON_OVERLAY_TEST 0x30004
-#define RADEON_OVERLAY_STATUS 0x30008
-#define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c
-#define RADEON_OVERLAY_GAMMA_5 0x30010
-#define RADEON_OVERLAY_GAMMA_4 0x30014
-#define RADEON_OVERLAY_GAMMA_3 0x30018
-#define RADEON_OVERLAY_GAMMA_2 0x3001c
-#define RADEON_OVERLAY_GAMMA_1 0x30020
-#define RADEON_OVERLAY_GAMMA_0 0x30024
-
-struct overlay_scale {
- uint32 _reserved0 : 3;
- uint32 horizontal_scale_fraction : 12;
- uint32 _reserved1 : 1;
- uint32 horizontal_downscale_factor : 3;
- uint32 _reserved2 : 1;
- uint32 vertical_scale_fraction : 12;
-};
-
-#define OVERLAY_FORMAT_RGB15 0x2
-#define OVERLAY_FORMAT_RGB16 0x3
-#define OVERLAY_FORMAT_RGB32 0x1
-#define OVERLAY_FORMAT_YCbCr422 0x8
-#define OVERLAY_FORMAT_YCbCr411 0x9
-#define OVERLAY_FORMAT_YCbCr420 0xc
-
-#define OVERLAY_MIRROR_NORMAL 0x0
-#define OVERLAY_MIRROR_HORIZONTAL 0x1
-#define OVERLAY_MIRROR_VERTICAL 0x2
-
-// The real overlay registers are written to using an update buffer
-
-struct overlay_registers {
- uint32 buffer_rgb0;
- uint32 buffer_rgb1;
- uint32 buffer_u0;
- uint32 buffer_v0;
- uint32 buffer_u1;
- uint32 buffer_v1;
- // (0x18) OSTRIDE - overlay stride
- uint16 stride_rgb;
- uint16 stride_uv;
- // (0x1c) YRGB_VPH - Y/RGB vertical phase
- uint16 vertical_phase0_rgb;
- uint16 vertical_phase1_rgb;
- // (0x20) UV_VPH - UV vertical phase
- uint16 vertical_phase0_uv;
- uint16 vertical_phase1_uv;
- // (0x24) HORZ_PH - horizontal phase
- uint16 horizontal_phase_rgb;
- uint16 horizontal_phase_uv;
- // (0x28) INIT_PHS - initial phase shift
- uint32 initial_vertical_phase0_shift_rgb0 : 4;
- uint32 initial_vertical_phase1_shift_rgb0 : 4;
- uint32 initial_horizontal_phase_shift_rgb0 : 4;
- uint32 initial_vertical_phase0_shift_uv : 4;
- uint32 initial_vertical_phase1_shift_uv : 4;
- uint32 initial_horizontal_phase_shift_uv : 4;
- uint32 _reserved0 : 8;
- // (0x2c) DWINPOS - destination window position
- uint16 window_left;
- uint16 window_top;
- // (0x30) DWINSZ - destination window size
- uint16 window_width;
- uint16 window_height;
- // (0x34) SWIDTH - source width
- uint16 source_width_rgb;
- uint16 source_width_uv;
- // (0x38) SWITDHSW - source width in 8 byte steps
- uint16 source_bytes_per_row_rgb;
- uint16 source_bytes_per_row_uv;
- uint16 source_height_rgb;
- uint16 source_height_uv;
- overlay_scale scale_rgb;
- overlay_scale scale_uv;
- // (0x48) OCLRC0 - overlay color correction 0
- uint32 brightness_correction : 8; // signed, -128 to 127
- uint32 _reserved1 : 10;
- uint32 contrast_correction : 9; // fixed point: 3.6 bits
- uint32 _reserved2 : 5;
- // (0x4c) OCLRC1 - overlay color correction 1
- uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
- uint32 _reserved3 : 6;
- uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
- uint32 _reserved4 : 5;
- // (0x50) DCLRKV - destination color key value
- uint32 color_key_blue : 8;
- uint32 color_key_green : 8;
- uint32 color_key_red : 8;
- uint32 _reserved5 : 8;
- // (0x54) DCLRKM - destination color key mask
- uint32 color_key_mask_blue : 8;
- uint32 color_key_mask_green : 8;
- uint32 color_key_mask_red : 8;
- uint32 _reserved6 : 7;
- uint32 color_key_enabled : 1;
- // (0x58) SCHRKVH - source chroma key high value
- uint32 source_chroma_key_high_red : 8;
- uint32 source_chroma_key_high_blue : 8;
- uint32 source_chroma_key_high_green : 8;
- uint32 _reserved7 : 8;
- // (0x5c) SCHRKVL - source chroma key low value
- uint32 source_chroma_key_low_red : 8;
- uint32 source_chroma_key_low_blue : 8;
- uint32 source_chroma_key_low_green : 8;
- uint32 _reserved8 : 8;
- // (0x60) SCHRKEN - source chroma key enable
- uint32 _reserved9 : 24;
- uint32 source_chroma_key_red_enabled : 1;
- uint32 source_chroma_key_blue_enabled : 1;
- uint32 source_chroma_key_green_enabled : 1;
- uint32 _reserved10 : 5;
- // (0x64) OCONFIG - overlay configuration
- uint32 _reserved11 : 3;
- uint32 color_control_output_mode : 1;
- uint32 yuv_to_rgb_bypass : 1;
- uint32 _reserved12 : 11;
- uint32 gamma2_enabled : 1;
- uint32 _reserved13 : 1;
- uint32 select_pipe : 1;
- uint32 slot_time : 8;
- uint32 _reserved14 : 5;
- // (0x68) OCOMD - overlay command
- uint32 overlay_enabled : 1;
- uint32 active_field : 1;
- uint32 active_buffer : 2;
- uint32 test_mode : 1;
- uint32 buffer_field_mode : 1;
- uint32 _reserved15 : 1;
- uint32 tv_flip_field_enabled : 1;
- uint32 _reserved16 : 1;
- uint32 tv_flip_field_parity : 1;
- uint32 source_format : 4;
- uint32 ycbcr422_order : 2;
- uint32 _reserved18 : 1;
- uint32 mirroring_mode : 2;
- uint32 _reserved19 : 13;
-
- uint32 _reserved20;
-
- uint32 start_0y;
- uint32 start_1y;
- uint32 start_0u;
- uint32 start_0v;
- uint32 start_1u;
- uint32 start_1v;
- uint32 _reserved21[6];
-#if 0
- // (0x70) AWINPOS - alpha blend window position
- uint32 awinpos;
- // (0x74) AWINSZ - alpha blend window size
- uint32 awinsz;
-
- uint32 _reserved21[10];
-#endif
-
- // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
- // the next two registers switch the usual Y/RGB vs. UV order)
- uint16 horizontal_scale_uv;
- uint16 horizontal_scale_rgb;
- // (0xa4) UVSCALEV - vertical downscale
- uint16 vertical_scale_uv;
- uint16 vertical_scale_rgb;
-
- uint32 _reserved22[86];
-
- // (0x200) polyphase filter coefficients
- uint16 vertical_coefficients_rgb[128];
- uint16 horizontal_coefficients_rgb[128];
-
- uint32 _reserved23[64];
-
- // (0x500)
- uint16 vertical_coefficients_uv[128];
- uint16 horizontal_coefficients_uv[128];
-};
-
-
-struct hardware_status {
- uint32 interrupt_status_register;
- uint32 _reserved0[3];
- void* primary_ring_head_storage;
- uint32 _reserved1[3];
- void* secondary_ring_0_head_storage;
- void* secondary_ring_1_head_storage;
- uint32 _reserved2[2];
- void* binning_head_storage;
- uint32 _reserved3[3];
- uint32 store[1008];
-};
#endif /* RADEON_HD_H */
