hrev53734 adds 1 changeset to branch 'master'
old head: a07c119825e1ee92d9b85a0e2d3a30b454ec432c
new head: 1808b553a21f326bbf4d9f64083158d90693f4e4
overview:
https://git.haiku-os.org/haiku/log/?qt=range&q=1808b553a21f+%5Ea07c119825e1
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1808b553a21f: intel_extreme: do not reprogram transcoded/output mapping on ibex
point
Another try to fix #15628
[ Adrien Destugues <pulkomandy@xxxxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev53734
Commit: 1808b553a21f326bbf4d9f64083158d90693f4e4
URL: https://git.haiku-os.org/haiku/commit/?id=1808b553a21f
Author: Adrien Destugues <pulkomandy@xxxxxxxxxxxxx>
Date: Sun Jan 19 10:03:12 2020 UTC
Ticket: https://dev.haiku-os.org/ticket/15628
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2 files changed, 26 insertions(+), 11 deletions(-)
.../graphics/intel_extreme/intel_extreme.h | 13 ++++++-----
src/add-ons/accelerants/intel_extreme/Ports.cpp | 24 ++++++++++++++++----
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diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h
b/headers/private/graphics/intel_extreme/intel_extreme.h
index 1982d9b390..b6c34e1946 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -491,6 +491,13 @@ struct intel_free_graphics_memory {
#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
#define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only
+// Cougar Point transcoder pipe selection
+// (replaces DISPLAY_MONITOR_PIPE_B)
+#define PORT_TRANS_A_SEL_CPT 0
+#define PORT_TRANS_B_SEL_CPT (1<<29)
+#define PORT_TRANS_C_SEL_CPT (2<<29)
+#define PORT_TRANS_SEL_MASK (3<<29)
+
#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
#define LVDS_POST2_RATE_FAST 7
#define LVDS_B0B3_POWER_MASK (3UL << 2)
@@ -552,12 +559,6 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_PIPE_SIZE (0x001c |
REGS_NORTH_PIPE_AND_PORT)
#define INTEL_DISPLAY_B_PIPE_SIZE (0x101c |
REGS_NORTH_PIPE_AND_PORT)
-// Cougar Point transcoder pipe selection
-#define PORT_TRANS_A_SEL_CPT 0
-#define PORT_TRANS_B_SEL_CPT (1<<29)
-#define PORT_TRANS_C_SEL_CPT (2<<29)
-#define PORT_TRANS_SEL_MASK (3<<29)
-
// on PCH we also have to set the transcoder
#define INTEL_TRANSCODER_A_HTOTAL (0x0000 |
REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_HBLANK (0x0004 |
REGS_SOUTH_TRANSCODER_PORT)
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp
b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index 5090984fc9..9037c3414c 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -372,12 +372,26 @@ LVDSPort::LVDSPort()
pipe_index
LVDSPort::PipePreference()
{
- // TODO: Technically INTEL_PIPE_B is only required on < gen 4
- // otherwise we can use INTEL_PIPE_ANY, however it seems to break
- // modesetting atm. (likely due to a bug on our end)
- //if (gInfo->shared_info->device_type.Generation() < 4)
- // return INTEL_PIPE_B;
+ // Older devices have hardcoded pipe/port mappings, so just use that
+ if (gInfo->shared_info->device_type.Generation() < 4)
+ return INTEL_PIPE_B;
+
+ // Ideally we could just return INTEL_PIPE_ANY for the newer devices,
but
+ // this doesn't quite work yet.
+
+ // For Ibex Point, read the existing LVDS configuration and just reuse
that
+ // (it seems our attempt to change it doesn't work, anyway)
+ if (gInfo->shared_info->pch_info == INTEL_PCH_IBX) {
+ uint32 portState = read32(_PortRegister());
+ if (portState & DISPLAY_MONITOR_PIPE_B)
+ return INTEL_PIPE_B;
+ else
+ return INTEL_PIPE_A;
+ }
+ // For later PCH versions, assume pipe B for now. Note that Cougar Point
+ // and probably later devices add a pipe C, so we'd need to handle that
+ // and the port register has a different format because of it.
return INTEL_PIPE_B;
}
