hrev50611 adds 1 changeset to branch 'master'
old head: be29847471cfb6323a2a0b65cce609ab218c8ab6
new head: bfb2f7ffc4475370087922d8962b547c1f58daeb
overview:
http://cgit.haiku-os.org/haiku/log/?qt=range&q=bfb2f7ffc447+%5Ebe29847471cf
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bfb2f7ffc447: intel_extreme: always set the base, surface and stride on both
pipes
Our code to assign outputs to pipes isn't working at the moment. Outputs
stay assigned to whatever the BIOS has set up. I tried to fix this but
didn't find a way yet (only more black screens).
As a workaround, always set both pipes A and B to always point to the
same frame buffer. This gets the display running properly on my Haswell
machine again, however mode setting is still not possible (so you can
only use the mode set by the BIOS).
[ Adrien Destugues <pulkomandy@xxxxxxxxx> ]
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Revision: hrev50611
Commit: bfb2f7ffc4475370087922d8962b547c1f58daeb
URL: http://cgit.haiku-os.org/haiku/commit/?id=bfb2f7ffc447
Author: Adrien Destugues <pulkomandy@xxxxxxxxx>
Date: Sat Oct 22 13:03:35 2016 UTC
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1 file changed, 17 insertions(+), 17 deletions(-)
src/add-ons/accelerants/intel_extreme/mode.cpp | 34 +++++++++++-----------
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diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp
b/src/add-ons/accelerants/intel_extreme/mode.cpp
index 3c4e05d..3034c60 100644
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -274,23 +274,12 @@ sanitize_display_mode(display_mode& mode)
// #pragma mark -
-void
-set_frame_buffer_base()
+static void set_frame_buffer_registers(uint32 baseRegister,
+ uint32 surfaceRegister)
{
intel_shared_info &sharedInfo = *gInfo->shared_info;
display_mode &mode = gInfo->current_mode;
- uint32 baseRegister;
- uint32 surfaceRegister;
-
- if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
- baseRegister = INTEL_DISPLAY_A_BASE;
- surfaceRegister = INTEL_DISPLAY_A_SURFACE;
- } else {
- baseRegister = INTEL_DISPLAY_B_BASE;
- surfaceRegister = INTEL_DISPLAY_B_SURFACE;
- }
-
if (sharedInfo.device_type.InGroup(INTEL_GROUP_96x)
|| sharedInfo.device_type.InGroup(INTEL_GROUP_G4x)
|| sharedInfo.device_type.InGroup(INTEL_GROUP_ILK)
@@ -310,6 +299,16 @@ set_frame_buffer_base()
}
+void
+set_frame_buffer_base()
+{
+ // TODO we always set both displays to the same address. When we support
+ // multiple framebuffers, they should get different addresses here.
+ set_frame_buffer_registers(INTEL_DISPLAY_A_BASE,
INTEL_DISPLAY_A_SURFACE);
+ set_frame_buffer_registers(INTEL_DISPLAY_B_BASE,
INTEL_DISPLAY_B_SURFACE);
+}
+
+
/*! Creates the initial mode list of the primary accelerant.
It's called from intel_init_accelerant().
*/
@@ -599,10 +598,11 @@ intel_set_display_mode(display_mode* mode)
// Changing bytes per row seems to be ignored if the plane/pipe is
turned
// off
- if (gInfo->head_mode & HEAD_MODE_A_ANALOG)
- write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow);
- if (gInfo->head_mode & HEAD_MODE_B_DIGITAL)
- write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow);
+ // Always set both pipes, just in case
+ // TODO rework this when we get multiple head support with different
+ // resolutions
+ write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow);
+ write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow);
// update shared info
gInfo->current_mode = target;
