[haiku-commits] haiku: hrev47487 - src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/dev/ath/ath_hal/ar9300
- From: jerome.duval@xxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Sat, 12 Jul 2014 14:45:28 +0200 (CEST)
hrev47487 adds 1 changeset to branch 'master'
old head: 712e51d79afaf96d4ccca91f3a2cd9197c98185d
new head: 57f444065f2636eb024651e1b55e56d4d4106034
overview: http://cgit.haiku-os.org/haiku/log/?qt=range&q=57f4440+%5E712e51d
----------------------------------------------------------------------------
57f4440: Update FreeBSD network drivers with the 9.3 release
[ Jérôme Duval <jerome.duval@xxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev47487
Commit: 57f444065f2636eb024651e1b55e56d4d4106034
URL: http://cgit.haiku-os.org/haiku/commit/?id=57f4440
Author: Jérôme Duval <jerome.duval@xxxxxxxxx>
Date: Sat Jul 12 12:31:01 2014 UTC
----------------------------------------------------------------------------
125 files changed, 248105 insertions(+), 297 deletions(-)
.../drivers/network/ar81xx/dev/ale/if_ale.c | 1 +
.../drivers/network/ar81xx/dev/ale/if_alevar.h | 2 +-
.../network/atheros813x/dev/alc/if_alcvar.h | 2 +-
.../network/attansic_l1/dev/age/if_agevar.h | 2 +-
.../drivers/network/attansic_l2/dev/ae/if_ae.c | 45 +-
.../network/attansic_l2/dev/ae/if_aereg.h | 2 +
.../network/broadcom570x/dev/bce/if_bcereg.h | 10 +-
.../network/broadcom570x/dev/bge/if_bge.c | 217 +-
.../network/broadcom570x/dev/bge/if_bgereg.h | 25 +-
.../network/broadcom570x/dev/mii/brgphy.c | 3 +
.../drivers/network/ipro100/dev/fxp/if_fxpreg.h | 2 +-
.../network/ipro1000/dev/e1000/e1000_defines.h | 2 +-
.../drivers/network/ipro1000/dev/e1000/if_em.c | 9 +-
.../drivers/network/ipro1000/dev/e1000/if_igb.c | 14 +-
.../drivers/network/ipro1000/dev/e1000/if_lem.c | 10 +-
.../network/jmicron2x0/dev/jme/if_jmevar.h | 2 +-
.../network/marvell_yukon/dev/msk/if_msk.c | 6 +-
.../network/marvell_yukon/dev/msk/if_mskreg.h | 2 +-
.../drivers/network/nforce/dev/nfe/if_nfe.c | 53 +-
.../drivers/network/nforce/dev/nfe/if_nfereg.h | 2 +-
.../kernel/drivers/network/pcnet/dev/le/am7990.c | 7 -
.../drivers/network/pcnet/dev/le/am79900.c | 7 -
.../drivers/network/pcnet/dev/le/am79900reg.h | 7 -
.../drivers/network/pcnet/dev/le/am7990reg.h | 7 -
.../drivers/network/pcnet/dev/le/if_le_pci.c | 7 -
.../kernel/drivers/network/pcnet/dev/le/lance.c | 7 -
.../drivers/network/pcnet/dev/le/lancereg.h | 7 -
.../drivers/network/syskonnect/dev/sk/if_sk.c | 7 -
.../network/wlan/aironetwifi/dev/an/if_an.c | 9 +-
.../wlan/aironetwifi/dev/an/if_an_pccard.c | 2 -
.../contrib/dev/ath/ath_hal/ar9300/ar9300.h | 1689 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_aic.c | 727 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c | 1278 +
.../ath/ath_hal/ar9300/ar9300_aphrodite10.ini | 1536 +
.../dev/ath/ath_hal/ar9300/ar9300_attach.c | 4120 +
.../dev/ath/ath_hal/ar9300/ar9300_beacon.c | 195 +
.../dev/ath/ath_hal/ar9300/ar9300_devid.h | 77 +
.../dev/ath/ath_hal/ar9300/ar9300_eeprom.c | 4538 +
.../dev/ath/ath_hal/ar9300/ar9300_freebsd.c | 675 +
.../dev/ath/ath_hal/ar9300/ar9300_freebsd.h | 82 +
.../dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h | 611 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c | 647 +
.../dev/ath/ath_hal/ar9300/ar9300_interrupts.c | 773 +
.../dev/ath/ath_hal/ar9300/ar9300_jupiter10.ini | 1894 +
.../dev/ath/ath_hal/ar9300/ar9300_jupiter20.ini | 2010 +
.../dev/ath/ath_hal/ar9300/ar9300_keycache.c | 438 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c | 1889 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c | 3765 +
.../dev/ath/ath_hal/ar9300/ar9300_osprey22.ini | 2188 +
.../ath_hal/ar9300/ar9300_osprey22_scoemu.ini | 2147 +
.../dev/ath/ath_hal/ar9300/ar9300_paprd.c | 2453 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c | 1212 +
.../dev/ath/ath_hal/ar9300/ar9300_power.c | 1554 +
.../dev/ath/ath_hal/ar9300/ar9300_radar.c | 601 +
.../dev/ath/ath_hal/ar9300/ar9300_radio.c | 267 +
.../ath/ath_hal/ar9300/ar9300_raw_adc_capture.c | 47 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c | 337 +
.../dev/ath/ath_hal/ar9300/ar9300_recv_ds.c | 195 +
.../dev/ath/ath_hal/ar9300/ar9300_reset.c | 6190 ++
.../contrib/dev/ath/ath_hal/ar9300/ar9300_rtt.c | 32 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_sim.c | 18 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_sim.h | 21 +
.../dev/ath/ath_hal/ar9300/ar9300_spectral.c | 588 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c | 171 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_stub.h | 7 +
.../dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c | 1256 +
.../dev/ath/ath_hal/ar9300/ar9300_stub_funcs.h | 237 +
.../dev/ath/ath_hal/ar9300/ar9300_timer.c | 181 +
.../dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c | 525 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_txbf.c | 30 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_txbf.h | 19 +
.../dev/ath/ath_hal/ar9300/ar9300_txbf_cal.c | 25 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c | 909 +
.../dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c | 959 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300desc.h | 587 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300eep.h | 709 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300paprd.h | 36 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300phy.h | 1955 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300radar.h | 45 +
.../contrib/dev/ath/ath_hal/ar9300/ar9300reg.h | 3119 +
.../ath/ath_hal/ar9300/ar9300template_ap121.h | 748 +
.../ath_hal/ar9300/ar9300template_aphrodite.h | 749 +
.../ath/ath_hal/ar9300/ar9300template_cus157.h | 737 +
.../ath/ath_hal/ar9300/ar9300template_generic.h | 748 +
.../ath/ath_hal/ar9300/ar9300template_hb112.h | 751 +
.../ath/ath_hal/ar9300/ar9300template_hb116.h | 751 +
.../ath_hal/ar9300/ar9300template_osprey_k31.h | 751 +
.../ath/ath_hal/ar9300/ar9300template_wasp_2.h | 747 +
.../ath/ath_hal/ar9300/ar9300template_wasp_k31.h | 748 +
.../ath/ath_hal/ar9300/ar9300template_xb112.h | 750 +
.../ath/ath_hal/ar9300/ar9300template_xb113.h | 750 +
.../contrib/dev/ath/ath_hal/ar9300/ar9330_11.ini | 1356 +
.../contrib/dev/ath/ath_hal/ar9300/ar9330_12.ini | 1289 +
.../contrib/dev/ath/ath_hal/ar9300/ar9340.ini | 4330 +
.../contrib/dev/ath/ath_hal/ar9300/ar9485.ini | 1419 +
.../dev/ath/ath_hal/ar9300/ar9485_1_1.ini | 1292 +
.../contrib/dev/ath/ath_hal/ar9300/ar955x.ini | 1684 +
.../contrib/dev/ath/ath_hal/ar9300/ar9580.ini | 2219 +
.../contrib/dev/ath/ath_hal/ar9300/eeprom.diff | 281 +
[ *** stats truncated: 26 lines dropped *** ]
----------------------------------------------------------------------------
diff --git a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c
b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c
index b5eb597..954a87f 100644
--- a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c
+++ b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c
@@ -1659,6 +1659,7 @@ ale_encap(struct ale_softc *sc, struct mbuf **m_head)
(mtod(m, intptr_t) & 3) != 0) {
m = m_defrag(*m_head, M_NOWAIT);
if (m == NULL) {
+ m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
diff --git a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_alevar.h
b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_alevar.h
index abf2d2e..8995c69 100644
--- a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_alevar.h
+++ b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_alevar.h
@@ -40,7 +40,7 @@
#define ALE_TSO_MAXSEGSIZE 4096
#define ALE_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
-#define ALE_MAXTXSEGS 32
+#define ALE_MAXTXSEGS 35
#define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
#define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32)
diff --git a/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alcvar.h
b/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alcvar.h
index b7c9d38..f2d806f 100644
--- a/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alcvar.h
+++ b/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alcvar.h
@@ -42,7 +42,7 @@
#define ALC_TSO_MAXSEGSIZE 4096
#define ALC_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
-#define ALC_MAXTXSEGS 32
+#define ALC_MAXTXSEGS 35
#define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
#define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32)
diff --git a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h
b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h
index 6ee5423..1479272 100644
--- a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h
+++ b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h
@@ -42,7 +42,7 @@
#define AGE_TSO_MAXSEGSIZE 4096
#define AGE_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
-#define AGE_MAXTXSEGS 32
+#define AGE_MAXTXSEGS 35
#define AGE_RX_BUF_ALIGN 8
#ifndef __NO_STRICT_ALIGNMENT
#define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN)
diff --git a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c
b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c
index 208a670..2244ebc 100644
--- a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c
+++ b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c
@@ -132,7 +132,7 @@ static void ae_mac_config(ae_softc_t *sc);
static int ae_intr(void *arg);
static void ae_int_task(void *arg, int pending);
static void ae_tx_intr(ae_softc_t *sc);
-static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
+static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
static void ae_rx_intr(ae_softc_t *sc);
static void ae_watchdog(ae_softc_t *sc);
static void ae_tick(void *arg);
@@ -585,7 +585,7 @@ ae_init_locked(ae_softc_t *sc)
val = eaddr[0] << 8 | eaddr[1];
AE_WRITE_4(sc, AE_EADDR1_REG, val);
- bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120);
+ bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING);
bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT);
bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4);
/*
@@ -1149,8 +1149,8 @@ ae_alloc_rings(ae_softc_t *sc)
*/
error = bus_dma_tag_create(sc->dma_parent_tag,
128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
- NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1,
- AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL,
+ NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1,
+ AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL,
&sc->dma_rxd_tag);
if (error != 0) {
device_printf(sc->dev, "could not creare TxS DMA tag.\n");
@@ -1209,15 +1209,15 @@ ae_alloc_rings(ae_softc_t *sc)
return (error);
}
error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
- sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb,
- &busaddr, BUS_DMA_NOWAIT);
+ sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING,
+ ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
if (error != 0 || busaddr == 0) {
device_printf(sc->dev,
"could not load DMA map for RxD ring.\n");
return (error);
}
- sc->dma_rxd_busaddr = busaddr + 120;
- sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120);
+ sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING;
+ sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING);
return (0);
}
@@ -1885,7 +1885,7 @@ ae_tx_intr(ae_softc_t *sc)
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
}
-static int
+static void
ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
{
struct ifnet *ifp;
@@ -1904,12 +1904,15 @@ ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
size = le16toh(rxd->len) - ETHER_CRC_LEN;
if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) {
if_printf(ifp, "Runt frame received.");
- return (EIO);
+ ifp->if_ierrors++;
+ return;
}
m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL);
- if (m == NULL)
- return (ENOBUFS);
+ if (m == NULL) {
+ ifp->if_iqdrops++;
+ return;
+ }
if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
(flags & AE_RXD_HAS_VLAN) != 0) {
@@ -1917,14 +1920,13 @@ ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
m->m_flags |= M_VLANTAG;
}
+ ifp->if_ipackets++;
/*
* Pass it through.
*/
AE_UNLOCK(sc);
(*ifp->if_input)(ifp, m);
AE_LOCK(sc);
-
- return (0);
}
static void
@@ -1933,7 +1935,7 @@ ae_rx_intr(ae_softc_t *sc)
ae_rxd_t *rxd;
struct ifnet *ifp;
uint16_t flags;
- int count, error;
+ int count;
KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
@@ -1961,17 +1963,10 @@ ae_rx_intr(ae_softc_t *sc)
*/
sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
- if ((flags & AE_RXD_SUCCESS) == 0) {
- ifp->if_ierrors++;
- continue;
- }
- error = ae_rxeof(sc, rxd);
- if (error != 0) {
+ if ((flags & AE_RXD_SUCCESS) != 0)
+ ae_rxeof(sc, rxd);
+ else
ifp->if_ierrors++;
- continue;
- } else {
- ifp->if_ipackets++;
- }
}
if (count > 0) {
diff --git a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_aereg.h
b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_aereg.h
index cc09e0b..4e0ae3b 100644
--- a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_aereg.h
+++ b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_aereg.h
@@ -104,6 +104,8 @@
#define AE_RXD_COUNT_MIN 16
#define AE_RXD_COUNT_MAX 512
#define AE_RXD_COUNT_DEFAULT 64
+/* Padding to align frames on a 128-byte boundary. */
+#define AE_RXD_PADDING 120
#define AE_TXD_BUFSIZE_MIN 4096
#define AE_TXD_BUFSIZE_MAX 65536
diff --git
a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h
b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h
index 8a156f5..b2b5928 100644
--- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h
+++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h
@@ -1,6 +1,5 @@
/*-
- * Copyright (c) 2006-2010 Broadcom Corporation
- * David Christensen <davidch@xxxxxxxxxxxx>. All rights reserved.
+ * Copyright (c) 2006-2014 QLogic Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -10,9 +9,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. Neither the name of Broadcom Corporation nor the name of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -6355,8 +6351,8 @@ struct fw_info {
#define BCE_TX_TIMEOUT 5
-#define BCE_MAX_SEGMENTS 32
-#define BCE_TSO_MAX_SIZE 65536
+#define BCE_MAX_SEGMENTS 35
+#define BCE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
#define BCE_TSO_MAX_SEG_SIZE 4096
#define BCE_DMA_ALIGN 8
diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c
b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c
index 7839cc5..3c65c4b 100644
--- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c
+++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c
@@ -176,6 +176,8 @@ static const struct bge_type {
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
@@ -195,6 +197,7 @@ static const struct bge_type {
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
@@ -217,11 +220,16 @@ static const struct bge_type {
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
{ BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
@@ -310,6 +318,7 @@ static const struct bge_revision {
{ BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
{ BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
{ BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
+ { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
{ BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
{ BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
/* 5754 and 5787 share the same ASIC ID */
@@ -354,6 +363,7 @@ static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM5717, "unknown BCM5717" },
{ BGE_ASICREV_BCM5719, "unknown BCM5719" },
{ BGE_ASICREV_BCM5720, "unknown BCM5720" },
+ { BGE_ASICREV_BCM5762, "unknown BCM5762" },
{ 0, NULL }
};
@@ -1802,6 +1812,20 @@ bge_chipinit(struct bge_softc *sc)
pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
}
+ if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM57766) {
+ /*
+ * For the 57766 and non Ax versions of 57765, bootcode
+ * needs to setup the PCIE Fast Training Sequence (FTS)
+ * value to prevent transmit hangs.
+ */
+ if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
+ CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
+ CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
+ BGE_CPMU_PADRNG_CTL_RDIV2);
+ }
+ }
+
/*
* Set up the PCI DMA control register.
*/
@@ -1877,8 +1901,9 @@ bge_chipinit(struct bge_softc *sc)
* a status tag update and leave interrupts permanently
* disabled.
*/
- if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
- sc->bge_asicrev != BGE_ASICREV_BCM57765)
+ if (!BGE_IS_57765_PLUS(sc) &&
+ sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
+ sc->bge_asicrev != BGE_ASICREV_BCM5762)
dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
}
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
@@ -1887,7 +1912,8 @@ bge_chipinit(struct bge_softc *sc)
* Set up general mode register.
*/
mode_ctl = bge_dma_swap_options(sc);
- if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762) {
/* Retain Host-2-BMC settings written by APE firmware. */
mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
(BGE_MODECTL_BYTESWAP_B2HRX_DATA |
@@ -1945,7 +1971,7 @@ bge_blockinit(struct bge_softc *sc)
struct bge_rcb *rcb;
bus_size_t vrcb;
bge_hostaddr taddr;
- uint32_t dmactl, val;
+ uint32_t dmactl, rdmareg, val;
int i, limit;
/*
@@ -2216,6 +2242,11 @@ bge_blockinit(struct bge_softc *sc)
if (!BGE_IS_5705_PLUS(sc))
/* 5700 to 5704 had 16 send rings. */
limit = BGE_TX_RINGS_EXTSSRAM_MAX;
+ else if (BGE_IS_57765_PLUS(sc) ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762)
+ limit = 2;
+ else if (BGE_IS_5717_PLUS(sc))
+ limit = 4;
else
limit = 1;
vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
@@ -2254,6 +2285,7 @@ bge_blockinit(struct bge_softc *sc)
} else if (!BGE_IS_5705_PLUS(sc))
limit = BGE_RX_RINGS_MAX;
else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
BGE_IS_57765_PLUS(sc))
limit = 4;
else
@@ -2293,7 +2325,8 @@ bge_blockinit(struct bge_softc *sc)
/* Set inter-packet gap */
val = 0x2620;
- if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762)
val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
(BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
@@ -2457,7 +2490,8 @@ bge_blockinit(struct bge_softc *sc)
val |= BGE_RDMAMODE_TSO6_ENABLE;
}
- if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762) {
val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
BGE_RDMAMODE_H2BNC_VLAN_DET;
/*
@@ -2471,14 +2505,18 @@ bge_blockinit(struct bge_softc *sc)
sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
- BGE_IS_5717_PLUS(sc)) {
- dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
+ BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
+ rdmareg = BGE_RDMA_RSRVCTRL_REG2;
+ else
+ rdmareg = BGE_RDMA_RSRVCTRL;
+ dmactl = CSR_READ_4(sc, rdmareg);
/*
* Adjust tx margin to prevent TX data corruption and
* fix internal FIFO overflow.
*/
- if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
- sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
+ if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762) {
dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
@@ -2491,7 +2529,7 @@ bge_blockinit(struct bge_softc *sc)
* The fix is to limit the number of RX BDs
* the hardware would fetch at a fime.
*/
- CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
+ CSR_WRITE_4(sc, rdmareg, dmactl |
BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
}
@@ -2509,11 +2547,34 @@ bge_blockinit(struct bge_softc *sc)
CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
+ } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
+ CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
+ CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
+ BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
+ BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
}
CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
DELAY(40);
+ if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
+ for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
+ val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
+ if ((val & 0xFFFF) > BGE_FRAMELEN)
+ break;
+ if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
+ break;
+ }
+ if (i != BGE_NUM_RDMA_CHANNELS / 2) {
+ val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
+ val |= BGE_RDMA_TX_LENGTH_WA_5719;
+ else
+ val |= BGE_RDMA_TX_LENGTH_WA_5720;
+ CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
+ }
+ }
+
/* Turn on RX data completion state machine */
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
@@ -2640,6 +2701,12 @@ bge_chipid(device_t dev)
case BCOM_DEVICEID_BCM5718:
case BCOM_DEVICEID_BCM5719:
case BCOM_DEVICEID_BCM5720:
+ case BCOM_DEVICEID_BCM5725:
+ case BCOM_DEVICEID_BCM5727:
+ case BCOM_DEVICEID_BCM5762:
+ case BCOM_DEVICEID_BCM57764:
+ case BCOM_DEVICEID_BCM57767:
+ case BCOM_DEVICEID_BCM57787:
id = pci_read_config(dev,
BGE_PCI_GEN2_PRODID_ASICREV, 4);
break;
@@ -2648,7 +2715,9 @@ bge_chipid(device_t dev)
case BCOM_DEVICEID_BCM57765:
case BCOM_DEVICEID_BCM57766:
case BCOM_DEVICEID_BCM57781:
+ case BCOM_DEVICEID_BCM57782:
case BCOM_DEVICEID_BCM57785:
+ case BCOM_DEVICEID_BCM57786:
case BCOM_DEVICEID_BCM57791:
case BCOM_DEVICEID_BCM57795:
id = pci_read_config(dev,
@@ -3271,7 +3340,7 @@ bge_attach(device_t dev)
struct bge_softc *sc;
uint32_t hwcfg = 0, misccfg, pcistate;
u_char eaddr[ETHER_ADDR_LEN];
- int capmask, error, msicount, reg, rid, trys;
+ int capmask, error, reg, rid, trys;
sc = device_get_softc(dev);
sc->bge_dev = dev;
@@ -3280,11 +3349,11 @@ bge_attach(device_t dev)
TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
- /*
- * Map control/status registers.
- */
pci_enable_busmaster(dev);
+ /*
+ * Allocate control/status registers.
+ */
rid = PCIR_BAR(0);
sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
@@ -3348,6 +3417,7 @@ bge_attach(device_t dev)
/* Save chipset family. */
switch (sc->bge_asicrev) {
+ case BGE_ASICREV_BCM5762:
case BGE_ASICREV_BCM57765:
case BGE_ASICREV_BCM57766:
sc->bge_flags |= BGE_FLAG_57765_PLUS;
@@ -3358,10 +3428,18 @@ bge_attach(device_t dev)
sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
BGE_FLAG_JUMBO_FRAME;
- if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
- sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
- /* Jumbo frame on BCM5719 A0 does not work. */
- sc->bge_flags &= ~BGE_FLAG_JUMBO;
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+ /*
+ * Enable work around for DMA engine miscalculation
+ * of TXMBUF available space.
+ */
+ sc->bge_flags |= BGE_FLAG_RDMA_BUG;
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
+ sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
+ /* Jumbo frame on BCM5719 A0 does not work. */
+ sc->bge_flags &= ~BGE_FLAG_JUMBO;
+ }
}
break;
case BGE_ASICREV_BCM5755:
@@ -3400,6 +3478,7 @@ bge_attach(device_t dev)
case BGE_ASICREV_BCM5719:
case BGE_ASICREV_BCM5720:
case BGE_ASICREV_BCM5761:
+ case BGE_ASICREV_BCM5762:
sc->bge_flags |= BGE_FLAG_APE;
break;
}
@@ -3584,13 +3663,8 @@ bge_attach(device_t dev)
rid = 0;
if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
sc->bge_msicap = reg;
- if (bge_can_use_msi(sc)) {
- msicount = pci_msi_count(dev);
- if (msicount > 1)
- msicount = 1;
- } else
- msicount = 0;
- if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
+ reg = 1;
+ if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
rid = 1;
sc->bge_flags |= BGE_FLAG_MSI;
}
@@ -3607,7 +3681,7 @@ bge_attach(device_t dev)
#endif
sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
- RF_SHAREABLE | RF_ACTIVE);
+ RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
if (sc->bge_irq == NULL) {
device_printf(sc->bge_dev, "couldn't map interrupt\n");
@@ -3950,20 +4024,19 @@ bge_release_resources(struct bge_softc *sc)
if (sc->bge_intrhand != NULL)
bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
- if (sc->bge_irq != NULL)
+ if (sc->bge_irq != NULL) {
bus_release_resource(dev, SYS_RES_IRQ,
- sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
-
- if (sc->bge_flags & BGE_FLAG_MSI)
+ rman_get_rid(sc->bge_irq), sc->bge_irq);
pci_release_msi(dev);
+ }
if (sc->bge_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY,
- PCIR_BAR(0), sc->bge_res);
+ rman_get_rid(sc->bge_res), sc->bge_res);
if (sc->bge_res2 != NULL)
bus_release_resource(dev, SYS_RES_MEMORY,
- PCIR_BAR(2), sc->bge_res2);
+ rman_get_rid(sc->bge_res2), sc->bge_res2);
if (sc->bge_ifp != NULL)
if_free(sc->bge_ifp);
@@ -4779,6 +4852,7 @@ bge_stats_update_regs(struct bge_softc *sc)
{
struct ifnet *ifp;
struct bge_mac_stats *stats;
+ uint32_t val;
ifp = sc->bge_ifp;
stats = &sc->bge_mac_stats;
@@ -4879,6 +4953,24 @@ bge_stats_update_regs(struct bge_softc *sc)
ifp->if_collisions = (u_long)stats->etherStatsCollisions;
ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
stats->InputErrors);
+
+ if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
+ /*
+ * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
+ * frames, it's safe to disable workaround for DMA engine's
+ * miscalculation of TXMBUF space.
+ */
+ if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
+ stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
+ val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
+ val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
+ else
+ val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
+ CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
+ sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
+ }
+ }
}
static void
@@ -5208,17 +5300,51 @@ bge_encap(struct bge_softc *sc, struct mbuf **m_head,
uint32_t *txidx)
csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
vlan_tag = m->m_pkthdr.ether_vtag;
}
- for (i = 0; ; i++) {
- d = &sc->bge_ldata.bge_tx_ring[idx];
- d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
- d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
- d->bge_len = segs[i].ds_len;
- d->bge_flags = csum_flags;
- d->bge_vlan_tag = vlan_tag;
- d->bge_mss = mss;
- if (i == nsegs - 1)
- break;
- BGE_INC(idx, BGE_TX_RING_CNT);
+
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
+ (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
+ /*
+ * 5725 family of devices corrupts TSO packets when TSO DMA
+ * buffers cross into regions which are within MSS bytes of
+ * a 4GB boundary. If we encounter the condition, drop the
+ * packet.
+ */
+ for (i = 0; ; i++) {
+ d = &sc->bge_ldata.bge_tx_ring[idx];
+ d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
+ d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
+ d->bge_len = segs[i].ds_len;
+ if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
+ d->bge_addr.bge_addr_lo)
+ break;
+ d->bge_flags = csum_flags;
+ d->bge_vlan_tag = vlan_tag;
+ d->bge_mss = mss;
+ if (i == nsegs - 1)
+ break;
+ BGE_INC(idx, BGE_TX_RING_CNT);
+ }
+ if (i != nsegs - 1) {
+ bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (EIO);
+ }
+ } else {
+ for (i = 0; ; i++) {
+ d = &sc->bge_ldata.bge_tx_ring[idx];
+ d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
+ d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
+ d->bge_len = segs[i].ds_len;
+ d->bge_flags = csum_flags;
+ d->bge_vlan_tag = vlan_tag;
+ d->bge_mss = mss;
+ if (i == nsegs - 1)
+ break;
+ BGE_INC(idx, BGE_TX_RING_CNT);
+ }
}
/* Mark the last segment as end of packet... */
@@ -5445,7 +5571,8 @@ bge_init_locked(struct bge_softc *sc)
mode = CSR_READ_4(sc, BGE_TX_MODE);
if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
- if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5762) {
mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
mode |= CSR_READ_4(sc, BGE_TX_MODE) &
(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
diff --git
a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h
b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h
index 50e6f45..6bebf56 100644
--- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h
+++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h
@@ -331,6 +331,7 @@
#define BGE_CHIPID_BCM5717_B0 0x05717100
#define BGE_CHIPID_BCM5719_A0 0x05719000
#define BGE_CHIPID_BCM5720_A0 0x05720000
+#define BGE_CHIPID_BCM5762_A0 0x05762000
#define BGE_CHIPID_BCM57765_A0 0x57785000
#define BGE_CHIPID_BCM57765_B0 0x57785100
@@ -357,6 +358,7 @@
#define BGE_ASICREV_BCM5719 0x5719
#define BGE_ASICREV_BCM5720 0x5720
#define BGE_ASICREV_BCM5761 0x5761
+#define BGE_ASICREV_BCM5762 0x5762
#define BGE_ASICREV_BCM5784 0x5784
#define BGE_ASICREV_BCM5785 0x5785
#define BGE_ASICREV_BCM57765 0x57785
@@ -378,6 +380,7 @@
#define BGE_CHIPREV_5717_AX 0x57170
#define BGE_CHIPREV_5717_BX 0x57171
#define BGE_CHIPREV_5761_AX 0x57611
+#define BGE_CHIPREV_57765_AX 0x577850
#define BGE_CHIPREV_5784_AX 0x57841
/* PCI DMA Read/Write Control register */
@@ -1289,6 +1292,7 @@
#define BGE_CPMU_MUTEX_REQ 0x365C
#define BGE_CPMU_MUTEX_GNT 0x3660
#define BGE_CPMU_PHY_STRAP 0x3664
+#define BGE_CPMU_PADRNG_CTL 0x3668
/* Central Power Management Unit (CPMU) register */
#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
@@ -1328,6 +1332,9 @@
/* CPMU GPHY Strap register */
#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
+/* CPMU Padring Control register */
+#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000
+
/*
* Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
*/
@@ -1539,6 +1546,8 @@
*/
#define BGE_RDMA_MODE 0x4800
#define BGE_RDMA_STATUS 0x4804
+#define BGE_RDMA_RSRVCTRL_REG2 0x4890
+#define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0
#define BGE_RDMA_RSRVCTRL 0x4900
#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910
@@ -1586,6 +1595,8 @@
#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000
#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000
+#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000
+#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000
/* BD Read DMA Mode register */
#define BGE_RDMA_BD_MODE 0x4A00
@@ -1603,6 +1614,9 @@
#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001
#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002
+#define BGE_RDMA_LENGTH 0x4BE0
+#define BGE_NUM_RDMA_CHANNELS 4
+
/*
* Write DMA control registers
*/
@@ -2444,6 +2458,8 @@ struct bge_status_block {
#define BCOM_DEVICEID_BCM5721 0x1659
#define BCOM_DEVICEID_BCM5722 0x165A
#define BCOM_DEVICEID_BCM5723 0x165B
+#define BCOM_DEVICEID_BCM5725 0x1643
+#define BCOM_DEVICEID_BCM5727 0x16F3
#define BCOM_DEVICEID_BCM5750 0x1676
#define BCOM_DEVICEID_BCM5750M 0x167C
#define BCOM_DEVICEID_BCM5751 0x1677
@@ -2463,6 +2479,7 @@ struct bge_status_block {
#define BCOM_DEVICEID_BCM5761E 0x1680
#define BCOM_DEVICEID_BCM5761S 0x1688
#define BCOM_DEVICEID_BCM5761SE 0x1689
+#define BCOM_DEVICEID_BCM5762 0x1687
#define BCOM_DEVICEID_BCM5764 0x1684
#define BCOM_DEVICEID_BCM5780 0x166A
#define BCOM_DEVICEID_BCM5780S 0x166B
@@ -2485,11 +2502,16 @@ struct bge_status_block {
#define BCOM_DEVICEID_BCM57760 0x1690
#define BCOM_DEVICEID_BCM57761 0x16B0
#define BCOM_DEVICEID_BCM57762 0x1682
+#define BCOM_DEVICEID_BCM57764 0x1642
#define BCOM_DEVICEID_BCM57765 0x16B4
#define BCOM_DEVICEID_BCM57766 0x1686
+#define BCOM_DEVICEID_BCM57767 0x1683
#define BCOM_DEVICEID_BCM57780 0x1692
#define BCOM_DEVICEID_BCM57781 0x16B1
+#define BCOM_DEVICEID_BCM57782 0x16B7
#define BCOM_DEVICEID_BCM57785 0x16B5
+#define BCOM_DEVICEID_BCM57786 0x16B3
+#define BCOM_DEVICEID_BCM57787 0x1641
#define BCOM_DEVICEID_BCM57788 0x1691
#define BCOM_DEVICEID_BCM57790 0x1694
#define BCOM_DEVICEID_BCM57791 0x16B2
@@ -2829,7 +2851,7 @@ struct bge_gib {
*/
#define BGE_NSEG_JUMBO 4
-#define BGE_NSEG_NEW 32
+#define BGE_NSEG_NEW 35
#define BGE_TSOSEG_SZ 4096
/* Maximum DMA address for controllers that have 40bit DMA address bug. */
@@ -2982,6 +3004,7 @@ struct bge_softc {
#define BGE_FLAG_SHORT_DMA_BUG 0x08000000
#define BGE_FLAG_4K_RDMA_BUG 0x10000000
#define BGE_FLAG_MBOX_REORDER 0x20000000
+#define BGE_FLAG_RDMA_BUG 0x40000000
uint32_t bge_mfw_flags; /* Management F/W flags */
#define BGE_MFW_ON_RXCPU 0x00000001
#define BGE_MFW_ON_APE 0x00000002
diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c
b/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c
index be4276c..dd29b34 100644
--- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c
+++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c
@@ -147,6 +147,7 @@ static const struct mii_phydesc brgphys[] = {
MII_PHY_DESC(BROADCOM3, BCM5720C),
MII_PHY_DESC(BROADCOM3, BCM57765),
MII_PHY_DESC(BROADCOM3, BCM57780),
+ MII_PHY_DESC(BROADCOM4, BCM5725C),
MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
MII_PHY_END
};
@@ -932,6 +933,8 @@ brgphy_reset(struct mii_softc *sc)
return;
}
break;
+ case MII_OUI_BROADCOM4:
+ return;
}
ifp = sc->mii_pdata->mii_ifp;
diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h
b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h
index cc764b5..7fd60af 100644
--- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h
+++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxpreg.h
@@ -250,7 +250,7 @@ struct fxp_cb_ucode {
/*
* Number of DMA segments in a TxCB.
*/
-#define FXP_NTXSEG 32
+#define FXP_NTXSEG 35
struct fxp_tbd {
uint32_t tb_addr;
diff --git
a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h
b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h
index 48c04b0..0815ea8 100644
--- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h
+++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h
@@ -129,7 +129,7 @@
#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits
*/
-#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
+#define E1000_RXDEXT_STATERR_TST 0x00010000 /* Time Stamp taken */
#define E1000_RXDEXT_STATERR_LB 0x00040000
#define E1000_RXDEXT_STATERR_CE 0x01000000
#define E1000_RXDEXT_STATERR_SE 0x02000000
diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c
b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c
index 09ef68e..1a53b4a 100644
--- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c
+++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c
@@ -3865,8 +3865,7 @@ em_txeof(struct tx_ring *txr)
EM_TX_LOCK_ASSERT(txr);
#ifdef DEV_NETMAP
- if (netmap_tx_irq(ifp, txr->me |
- (NETMAP_LOCKED_ENTER | NETMAP_LOCKED_EXIT)))
+ if (netmap_tx_irq(ifp, txr->me))
return;
#endif /* DEV_NETMAP */
@@ -4399,7 +4398,7 @@ em_initialize_receive_unit(struct adapter *adapter)
* preserve the rx buffers passed to userspace.
*/
if (ifp->if_capenable & IFCAP_NETMAP)
- rdt -= NA(adapter->ifp)->rx_rings[i].nr_hwavail;
+ rdt -= nm_kr_rxspace(&NA(adapter->ifp)->rx_rings[i]);
#endif /* DEV_NETMAP */
E1000_WRITE_REG(hw, E1000_RDT(i), rdt);
}
@@ -4478,8 +4477,10 @@ em_rxeof(struct rx_ring *rxr, int count, int *done)
EM_RX_LOCK(rxr);
#ifdef DEV_NETMAP
- if (netmap_rx_irq(ifp, rxr->me | NETMAP_LOCKED_ENTER, &processed))
+ if (netmap_rx_irq(ifp, rxr->me, &processed)) {
+ EM_RX_UNLOCK(rxr);
return (FALSE);
+ }
#endif /* DEV_NETMAP */
for (i = rxr->next_to_check, processed = 0; count != 0;) {
diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c
b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c
index 6887bcf..196323d 100644
--- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c
+++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c
@@ -2883,6 +2883,9 @@ igb_setup_msix(struct adapter *adapter)
if (queues > maxqueues)
queues = maxqueues;
+ /* reflect correct sysctl value */
+ igb_num_queues = queues;
+
/*
** One vector (RX/TX pair) per queue
** plus an additional for Link interrupt
@@ -3907,8 +3910,7 @@ igb_txeof(struct tx_ring *txr)
IGB_TX_LOCK_ASSERT(txr);
#ifdef DEV_NETMAP
- if (netmap_tx_irq(ifp, txr->me |
- (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
+ if (netmap_tx_irq(ifp, txr->me ))
return (FALSE);
#endif /* DEV_NETMAP */
if (txr->tx_avail == adapter->num_tx_desc) {
@@ -4569,13 +4571,13 @@ igb_initialize_receive_units(struct adapter *adapter)
* an init() while a netmap client is active must
* preserve the rx buffers passed to userspace.
* In this driver it means we adjust RDT to
- * somthing different from next_to_refresh
+ * something different from next_to_refresh
* (which is not used in netmap mode).
*/
if (ifp->if_capenable & IFCAP_NETMAP) {
struct netmap_adapter *na = NA(adapter->ifp);
struct netmap_kring *kring = &na->rx_rings[i];
- int t = rxr->next_to_refresh - kring->nr_hwavail;
+ int t = rxr->next_to_refresh - nm_kr_rxspace(kring);
if (t >= adapter->num_rx_desc)
t -= adapter->num_rx_desc;
@@ -4763,8 +4765,10 @@ igb_rxeof(struct igb_queue *que, int count, int *done)
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
#ifdef DEV_NETMAP
- if (netmap_rx_irq(ifp, rxr->me | NETMAP_LOCKED_ENTER, &processed))
+ if (netmap_rx_irq(ifp, rxr->me, &processed)) {
+ IGB_RX_UNLOCK(rxr);
return (FALSE);
+ }
#endif /* DEV_NETMAP */
/* Main clean loop */
diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c
b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c
index 6569145..1741c38 100644
--- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c
+++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c
@@ -2716,7 +2716,7 @@ lem_setup_transmit_structures(struct adapter *adapter)
void *addr;
addr = PNMB(slot + si, &paddr);
- adapter->tx_desc_base[si].buffer_addr = htole64(paddr);
+ adapter->tx_desc_base[i].buffer_addr = htole64(paddr);
/* reload the map for netmap mode */
netmap_load_map(adapter->txtag, tx_buffer->map, addr);
}
@@ -3030,7 +3030,7 @@ lem_txeof(struct adapter *adapter)
EM_TX_LOCK_ASSERT(adapter);
#ifdef DEV_NETMAP
- if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
+ if (netmap_tx_irq(ifp, 0))
return;
#endif /* DEV_NETMAP */
if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
@@ -3413,7 +3413,7 @@ lem_initialize_receive_unit(struct adapter *adapter)
#ifdef DEV_NETMAP
/* preserve buffers already made available to clients */
if (ifp->if_capenable & IFCAP_NETMAP)
- rctl -= NA(adapter->ifp)->rx_rings[0].nr_hwavail;
+ rctl -= nm_kr_rxspace(&NA(adapter->ifp)->rx_rings[0]);
#endif /* DEV_NETMAP */
E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), rctl);
@@ -3499,8 +3499,10 @@ lem_rxeof(struct adapter *adapter, int count, int *done)
BUS_DMASYNC_POSTREAD);
#ifdef DEV_NETMAP
- if (netmap_rx_irq(ifp, 0 | NETMAP_LOCKED_ENTER, &rx_sent))
+ if (netmap_rx_irq(ifp, 0, &rx_sent)) {
+ EM_RX_UNLOCK(adapter);
return (FALSE);
+ }
#endif /* DEV_NETMAP */
if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
diff --git a/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmevar.h
b/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmevar.h
index eb4eddc..1a1e81c 100644
--- a/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmevar.h
+++ b/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmevar.h
@@ -49,7 +49,7 @@
#define JME_RX_RING_ALIGN 16
#define JME_TSO_MAXSEGSIZE 4096
#define JME_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
-#define JME_MAXTXSEGS 32
+#define JME_MAXTXSEGS 35
#define JME_RX_BUF_ALIGN sizeof(uint64_t)
#define JME_SSB_ALIGN 16
diff --git a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c
b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c
index 4c26fc8..8f601a3 100644
--- a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c
+++ b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c
@@ -4078,12 +4078,12 @@ msk_init_locked(struct msk_if_softc *sc_if)
CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
CSR_READ_4(sc, B0_IMSK);
- sc_if->msk_flags &= ~MSK_FLAG_LINK;
- mii_mediachg(mii);
-
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ sc_if->msk_flags &= ~MSK_FLAG_LINK;
+ mii_mediachg(mii);
+
callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
}
diff --git
a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_mskreg.h
b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_mskreg.h
index 3037797..2602764 100644
--- a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_mskreg.h
+++ b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_mskreg.h
@@ -2338,7 +2338,7 @@ struct msk_stat_desc {
#endif
#define MSK_RX_BUF_ALIGN 8
#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT
-#define MSK_MAXTXSEGS 32
+#define MSK_MAXTXSEGS 35
#define MSK_TSO_MAXSGSIZE 4096
#define MSK_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
index 04aeb06..bfc93d3 100644
--- a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
+++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
@@ -78,6 +78,7 @@ static int nfe_suspend(device_t);
static int nfe_resume(device_t);
static int nfe_shutdown(device_t);
static int nfe_can_use_msix(struct nfe_softc *);
+static int nfe_detect_msik9(struct nfe_softc *);
static void nfe_power(struct nfe_softc *);
static int nfe_miibus_readreg(device_t, int, int);
static int nfe_miibus_writereg(device_t, int, int, int);
@@ -333,13 +334,38 @@ nfe_alloc_msix(struct nfe_softc *sc, int count)
}
}
+
+static int
+nfe_detect_msik9(struct nfe_softc *sc)
+{
+ static const char *maker = "MSI";
+ static const char *product = "K9N6PGM2-V2 (MS-7309)";
+ char *m, *p;
+ int found;
+
+ found = 0;
+ m = getenv("smbios.planar.maker");
+ p = getenv("smbios.planar.product");
+ if (m != NULL && p != NULL) {
+ if (strcmp(m, maker) == 0 && strcmp(p, product) == 0)
+ found = 1;
+ }
+ if (m != NULL)
+ freeenv(m);
+ if (p != NULL)
+ freeenv(p);
+
+ return (found);
+}
+
+
static int
nfe_attach(device_t dev)
{
struct nfe_softc *sc;
struct ifnet *ifp;
bus_addr_t dma_addr_max;
- int error = 0, i, msic, reg, rid;
+ int error = 0, i, msic, phyloc, reg, rid;
sc = device_get_softc(dev);
sc->nfe_dev = dev;
@@ -608,8 +634,16 @@ nfe_attach(device_t dev)
#endif
/* Do MII setup */
+ phyloc = MII_PHY_ANY;
+ if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 ||
+ sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 ||
+ sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 ||
+ sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) {
+ if (nfe_detect_msik9(sc) != 0)
+ phyloc = 0;
+ }
error = mii_attach(dev, &sc->nfe_miibus, ifp, nfe_ifmedia_upd,
- nfe_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
+ nfe_ifmedia_sts, BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY,
MIIF_DOPAUSE);
if (error != 0) {
device_printf(dev, "attaching PHYs failed\n");
@@ -1342,15 +1376,12 @@ nfe_free_rx_ring(struct nfe_softc *sc, struct
nfe_rx_ring *ring)
{
struct nfe_rx_data *data;
void *desc;
- int i, descsize;
+ int i;
- if (sc->nfe_flags & NFE_40BIT_ADDR) {
+ if (sc->nfe_flags & NFE_40BIT_ADDR)
desc = ring->desc64;
- descsize = sizeof (struct nfe_desc64);
- } else {
+ else
desc = ring->desc32;
- descsize = sizeof (struct nfe_desc32);
- }
for (i = 0; i < NFE_RX_RING_COUNT; i++) {
data = &ring->data[i];
@@ -3206,8 +3237,8 @@ nfe_stats_clear(struct nfe_softc *sc)
else
return;
- for (i = 0; i < mib_cnt; i += sizeof(uint32_t))
- NFE_READ(sc, NFE_TX_OCTET + i);
+ for (i = 0; i < mib_cnt; i++)
+ NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t));
if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
NFE_READ(sc, NFE_TX_UNICAST);
@@ -3261,7 +3292,7 @@ nfe_stats_update(struct nfe_softc *sc)
if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST);
stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST);
- stats->rx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST);
+ stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST);
}
}
diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
index 59c88c7..748c25b 100644
--- a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
+++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
@@ -40,7 +40,7 @@
(NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
-#define NFE_MAX_SCATTER 32
+#define NFE_MAX_SCATTER 35
#define NFE_TSO_MAXSGSIZE 4096
#define NFE_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990.c
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990.c
index 56a07d5..d74d3b8 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990.c
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990.c
@@ -16,13 +16,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900.c
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900.c
index a86590b..a31fe70 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900.c
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900.c
@@ -15,13 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900reg.h
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900reg.h
index 3361064..620a1dd 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900reg.h
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am79900reg.h
@@ -15,13 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990reg.h
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990reg.h
index d3f8e0d..1cc4dcb 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990reg.h
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/am7990reg.h
@@ -15,13 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/if_le_pci.c
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/if_le_pci.c
index b989fe0..1146472 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/if_le_pci.c
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/if_le_pci.c
@@ -16,13 +16,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c
index e2cc30e..da433a7 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c
@@ -16,13 +16,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lancereg.h
b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lancereg.h
index 3e0ce06..7c1a5a8 100644
--- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lancereg.h
+++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lancereg.h
@@ -15,13 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
diff --git a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c
b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c
index e0394ae..bfca0ca 100644
--- a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c
+++ b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c
@@ -138,11 +138,6 @@ MODULE_DEPEND(sk, miibus, 1, 1, 1);
/* "device miibus" required. See GENERIC if you get errors here. */
#include "miibus_if.h"
-#ifndef lint
-static const char rcsid[] =
- "$FreeBSD$";
-#endif
-
static const struct sk_type sk_devs[] = {
{
VENDORID_SK,
@@ -2899,13 +2894,11 @@ static void
sk_txeof(sc_if)
struct sk_if_softc *sc_if;
{
- struct sk_softc *sc;
struct sk_txdesc *txd;
struct sk_tx_desc *cur_tx;
struct ifnet *ifp;
u_int32_t idx, sk_ctl;
- sc = sc_if->sk_softc;
ifp = sc_if->sk_ifp;
txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
diff --git a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c
b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c
index 0a195a6..a583023 100644
--- a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c
+++ b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c
@@ -357,6 +357,7 @@ an_probe(device_t dev)
CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
+ sc->an_dev = dev;
mtx_init(&sc->an_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
AN_LOCK(sc);
@@ -685,6 +686,9 @@ an_attach(struct an_softc *sc, int flags)
device_printf(sc->an_dev, "can not if_alloc()\n");
goto fail;
}
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(sc->an_dev),
+ device_get_unit(sc->an_dev));
sc->an_gone = 0;
sc->an_associated = 0;
@@ -758,9 +762,6 @@ an_attach(struct an_softc *sc, int flags)
#endif
AN_UNLOCK(sc);
- ifp->if_softc = sc;
- if_initname(ifp, device_get_name(sc->an_dev),
- device_get_unit(sc->an_dev));
ifp->if_mtu = ETHERMTU;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = an_ioctl;
@@ -1388,7 +1389,7 @@ an_reset(struct an_softc *sc)
an_cmd(sc, AN_CMD_NOOP2, 0);
if (an_cmd(sc, AN_CMD_FORCE_SYNCLOSS, 0) == ETIMEDOUT)
- if_printf(sc->an_ifp, "reset failed\n");
+ device_printf(sc->an_dev, "reset failed\n");
an_cmd(sc, AN_CMD_DISABLE, 0);
diff --git
a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pccard.c
b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pccard.c
index bdd40f3..e9485ea 100644
--- a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pccard.c
+++ b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pccard.c
@@ -141,8 +141,6 @@ an_pccard_attach(device_t dev)
an_alloc_irq(dev, sc->irq_rid, 0);
- sc->an_dev = dev;
-
error = an_attach(sc, flags);
if (error)
goto fail;
diff --git
a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/dev/ath/ath_hal/ar9300/ar9300.h
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/dev/ath/ath_hal/ar9300/ar9300.h
new file mode 100644
index 0000000..73b902f
--- /dev/null
+++
b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/dev/ath/ath_hal/ar9300/ar9300.h
@@ -0,0 +1,1689 @@
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
OR
+ * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ATH_AR9300_H_
+#define _ATH_AR9300_H_
+
+#include "ar9300_freebsd_inc.h"
+
+#define AH_BIG_ENDIAN 4321
+#define AH_LITTLE_ENDIAN 1234
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+#define AH_BYTE_ORDER AH_BIG_ENDIAN
+#else
+#define AH_BYTE_ORDER AH_LITTLE_ENDIAN
+#endif
+
+/* XXX doesn't belong here */
+#define AR_EEPROM_MODAL_SPURS 5
+
+/*
+ * (a) this should be N(a),
+ * (b) FreeBSD does define nitems,
+ * (c) it doesn't have an AH_ prefix, sigh.
+ */
+#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0]))
+
+#include "ah_internal.h"
+#include "ah_eeprom.h"
+#include "ah_devid.h"
+#include "ar9300eep.h" /* For Eeprom definitions */
+
+
+#define AR9300_MAGIC 0x19741014
+
+
+/* MAC register values */
+
+#define INIT_CONFIG_STATUS 0x00000000
+#define INIT_RSSI_THR 0x7 /* Missed beacon counter
initialized to 0x7 (max is 0xff) */
+#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */
+
+/*
+ * Various fifo fill before Tx start, in 64-byte units
+ * i.e. put the frame in the air while still DMAing
+ */
+#define MIN_TX_FIFO_THRESHOLD 0x1
+#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1)
+#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
+
+ #define CHANSEL_DIV 15
+ #define FCLK 40
+
+#define COEFF ((FCLK * 5) / 2)
+#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
+#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
+#define CHANSEL_5G_DOT5MHZ 2188
+
+/*
+ * Receive Queue Fifo depth.
+ */
+enum RX_FIFO_DEPTH {
+ HAL_HP_RXFIFO_DEPTH = 16,
+ HAL_LP_RXFIFO_DEPTH = 128,
+};
+
+/*
+ * Gain support.
+ */
+#define NUM_CORNER_FIX_BITS_2133 7
+#define CCK_OFDM_GAIN_DELTA 15
+
+enum GAIN_PARAMS {
+ GP_TXCLIP,
+ GP_PD90,
+ GP_PD84,
+ GP_GSEL
+};
+
+enum GAIN_PARAMS_2133 {
+ GP_MIXGAIN_OVR,
+ GP_PWD_138,
+ GP_PWD_137,
+ GP_PWD_136,
+ GP_PWD_132,
+ GP_PWD_131,
+ GP_PWD_130,
+};
+
+enum {
+ HAL_RESET_POWER_ON,
+ HAL_RESET_WARM,
+ HAL_RESET_COLD,
+};
+
+typedef struct _gain_opt_step {
+ int16_t paramVal[NUM_CORNER_FIX_BITS_2133];
+ int32_t stepGain;
+ int8_t stepName[16];
+} GAIN_OPTIMIZATION_STEP;
+
+typedef struct {
+ u_int32_t numStepsInLadder;
+ u_int32_t defaultStepNum;
+ GAIN_OPTIMIZATION_STEP optStep[10];
+} GAIN_OPTIMIZATION_LADDER;
+
+typedef struct {
+ u_int32_t currStepNum;
+ u_int32_t currGain;
+ u_int32_t targetGain;
+ u_int32_t loTrig;
+ u_int32_t hiTrig;
+ u_int32_t gainFCorrection;
+ u_int32_t active;
+ GAIN_OPTIMIZATION_STEP *curr_step;
+} GAIN_VALUES;
+
+typedef struct {
+ u_int16_t synth_center;
+ u_int16_t ctl_center;
+ u_int16_t ext_center;
+} CHAN_CENTERS;
+
+/* RF HAL structures */
+typedef struct rf_hal_funcs {
+ HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *);
+ HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah,
+ struct ieee80211_channel *chan);
+} RF_HAL_FUNCS;
+
+struct ar9300_ani_default {
+ u_int16_t m1_thresh_low;
+ u_int16_t m2_thresh_low;
+ u_int16_t m1_thresh;
+ u_int16_t m2_thresh;
+ u_int16_t m2_count_thr;
+ u_int16_t m2_count_thr_low;
+ u_int16_t m1_thresh_low_ext;
+ u_int16_t m2_thresh_low_ext;
+ u_int16_t m1_thresh_ext;
+ u_int16_t m2_thresh_ext;
+ u_int16_t firstep;
+ u_int16_t firstep_low;
+ u_int16_t cycpwr_thr1;
+ u_int16_t cycpwr_thr1_ext;
+};
+
+/*
+ * Per-channel ANI state private to the driver.
+ */
+struct ar9300_ani_state {
+ struct ieee80211_channel c; /* XXX ew? */
+ HAL_BOOL must_restore;
+ HAL_BOOL ofdms_turn;
+ u_int8_t ofdm_noise_immunity_level;
+ u_int8_t cck_noise_immunity_level;
+ u_int8_t spur_immunity_level;
+ u_int8_t firstep_level;
+ u_int8_t ofdm_weak_sig_detect_off;
+ u_int8_t mrc_cck_off;
+
+ /* Thresholds */
+ u_int32_t listen_time;
+ u_int32_t ofdm_trig_high;
+ u_int32_t ofdm_trig_low;
+ int32_t cck_trig_high;
+ int32_t cck_trig_low;
+ int32_t rssi_thr_low;
+ int32_t rssi_thr_high;
+
+ int32_t rssi; /* The current RSSI */
+ u_int32_t tx_frame_count; /* Last tx_frame_count */
+ u_int32_t rx_frame_count; /* Last rx Frame count */
+ u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */
+ u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */
+ u_int32_t cck_phy_err_count; /* CCK err count since last reset */
+
+ struct ar9300_ani_default ini_def; /* INI default values for ANI
registers */
+ HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */
+};
+
+#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI
poll */
+
+#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to
change channels */
+
+#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */
+#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */
+#define HAL_AR_EN 0x40000000 /* AR detect is capable */
+
+#define DO_ANI(ah) \
+ ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI))
+
+struct ar9300_stats {
+ u_int32_t ast_ani_niup; /* ANI increased noise immunity */
+ u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */
+ u_int32_t ast_ani_spurup; /* ANI increased spur immunity */
+ u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */
+ u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
+ u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
+ u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
+ u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
+ u_int32_t ast_ani_stepup; /* ANI increased first step level */
+ u_int32_t ast_ani_stepdown;/* ANI decreased first step level */
+ u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
+ u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
+ u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
+ u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */
+ u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
+ HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
+ HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
+};
+
+struct ar9300_rad_reader {
+ u_int16_t rd_index;
+ u_int16_t rd_expSeq;
+ u_int32_t rd_resetVal;
+ u_int8_t rd_start;
+};
+
+struct ar9300_rad_writer {
+ u_int16_t wr_index;
+ u_int16_t wr_seq;
+};
+
+struct ar9300_radar_event {
+ u_int32_t re_ts; /* 32 bit time stamp */
+ u_int8_t re_rssi; /* rssi of radar event */
+ u_int8_t re_dur; /* duration of radar pulse */
+ u_int8_t re_chanIndex; /* Channel of event */
+};
+
+struct ar9300_radar_q_elem {
+ u_int32_t rq_seqNum;
+ u_int32_t rq_busy; /* 32 bit to insure atomic read/write */
+ struct ar9300_radar_event rq_event; /* Radar event */
+};
+
+struct ar9300_radar_q_info {
+ u_int16_t ri_qsize; /* q size */
+ u_int16_t ri_seqSize; /* Size of sequence ring */
+ struct ar9300_rad_reader ri_reader; /* State for the q reader */
+ struct ar9300_rad_writer ri_writer; /* state for the q writer */
+};
+
+#define HAL_MAX_ACK_RADAR_DUR 511
+#define HAL_MAX_NUM_PEAKS 3
+#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */
+#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */
+#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */
+#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */
+#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state
for */
+
+struct ar9300_ar_state {
+ u_int16_t ar_prev_time_stamp;
+ u_int32_t ar_prev_width;
+ u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR];
+ u_int32_t ar_ack_sum;
+ u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS];
+ u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */
+ u_int32_t ar_par_threshold; /* Thresh to determine peak */
+ u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */
+};
+
+struct ar9300_radar_state {
+ struct ieee80211_channel *rs_chan; /* Channel info */
+ u_int8_t rs_chan_index; /* Channel index in radar structure */
+ u_int32_t rs_num_radar_events; /* Number of radar events */
+ int32_t rs_firpwr; /* Thresh to check radar sig is gone */
+ u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */
+ u_int32_t rs_height; /* Thresh for pulse height (dB)*/
+ u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB)
*/
+ u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB)
*/
+};
+typedef struct {
+ u_int8_t uc_receiver_errors;
+ u_int8_t uc_bad_tlp_errors;
+ u_int8_t uc_bad_dllp_errors;
+ u_int8_t uc_replay_timeout_errors;
+ u_int8_t uc_replay_number_rollover_errors;
+} ar_pcie_error_moniter_counters;
+
+#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */
+#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */
+#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */
+#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */
+#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */
+#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */
+
+/*
+ * For Kite and later chipsets, the following bits are not being programmed in
EEPROM
+ * and so need to be enabled always.
+ * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40
+ * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40
+ */
+#define AR9300_RDEXT_DEFAULT 0x1F
+
+#define AR9300_MAX_CHAINS 3
+#define AR9300_NUM_CHAINS(chainmask) \
+ (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1))
+#define AR9300_CHAIN0_MASK 0x1
+#define AR9300_CHAIN1_MASK 0x2
+#define AR9300_CHAIN2_MASK 0x4
+
+/* Support for multiple INIs */
+struct ar9300_ini_array {
+ u_int32_t *ia_array;
+ u_int32_t ia_rows;
+ u_int32_t ia_columns;
+};
+#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
+ (iniarray)->ia_array = (u_int32_t *)(array); \
+ (iniarray)->ia_rows = (rows); \
+ (iniarray)->ia_columns = (columns); \
+} while (0)
+#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) *
((iniarray)->ia_columns) + (column)])
+
+#define INIT_CAL(_perCal) \
+ (_perCal)->cal_state = CAL_WAITING; \
+ (_perCal)->cal_next = AH_NULL;
+
+#define INSERT_CAL(_ahp, _perCal) \
+do { \
+ if ((_ahp)->ah_cal_list_last == AH_NULL) { \
+ (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \
+ ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \
+ } else { \
+ ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \
+ (_ahp)->ah_cal_list_last = (_perCal); \
+ (_perCal)->cal_next = (_ahp)->ah_cal_list; \
+ } \
+} while (0)
+
+typedef enum cal_types {
+ IQ_MISMATCH_CAL = 0x1,
+ TEMP_COMP_CAL = 0x2,
+} HAL_CAL_TYPES;
+
+typedef enum cal_state {
+ CAL_INACTIVE,
+ CAL_WAITING,
+ CAL_RUNNING,
+ CAL_DONE
+} HAL_CAL_STATE; /* Calibrate state */
+
+#define MIN_CAL_SAMPLES 1
+#define MAX_CAL_SAMPLES 64
+#define INIT_LOG_COUNT 5
+#define PER_MIN_LOG_COUNT 2
+#define PER_MAX_LOG_COUNT 10
+
+#define AR9300_NUM_BT_WEIGHTS 4
+#define AR9300_NUM_WLAN_WEIGHTS 4
+
+/* Per Calibration data structure */
+typedef struct per_cal_data {
+ HAL_CAL_TYPES cal_type; // Type of calibration
+ u_int32_t cal_num_samples; // Number of SW samples to collect
+ u_int32_t cal_count_max; // Number of HW samples to collect
+ void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func
+ void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func
+} HAL_PERCAL_DATA;
+
+/* List structure for calibration data */
+typedef struct cal_list {
+ const HAL_PERCAL_DATA *cal_data;
+ HAL_CAL_STATE cal_state;
+ struct cal_list *cal_next;
+} HAL_CAL_LIST;
+
+#define AR9300_NUM_CAL_TYPES 2
+#define AR9300_PAPRD_TABLE_SZ 24
+#define AR9300_PAPRD_GAIN_TABLE_SZ 32
+#define AR9382_MAX_GPIO_PIN_NUM (16)
+#define AR9382_GPIO_PIN_8_RESERVED (8)
+#define AR9382_GPIO_9_INPUT_ONLY (9)
+#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13)
+#define AR9382_GPIO_PIN_11_RESERVED (11)
+#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3)
+
+/* Paprd tx power adjust data structure */
+struct ar9300_paprd_pwr_adjust {
+ u_int32_t target_rate; // rate index
+ u_int32_t reg_addr; // register offset
+ u_int32_t reg_mask; // mask of register
+ u_int32_t reg_mask_offset; // mask offset of register
+ u_int32_t sub_db; // offset value unit of dB
+};
+
+struct ar9300NfLimits {
+ int16_t max;
+ int16_t min;
+ int16_t nominal;
+};
+
+#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) +
HTTS(8)*/
+struct ath_hal_9300 {
+ struct ath_hal_private ah_priv; /* base class */
+
+ /*
+ * Information retrieved from EEPROM.
+ */
+ ar9300_eeprom_t ah_eeprom;
+
+ GAIN_VALUES ah_gain_values;
+
+ u_int8_t ah_macaddr[IEEE80211_ADDR_LEN];
+ u_int8_t ah_bssid[IEEE80211_ADDR_LEN];
+ u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN];
+ u_int16_t ah_assoc_id;
+
+ /*
+ * Runtime state.
+ */
+ u_int32_t ah_mask_reg; /* copy of AR_IMR */
+ u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */
+ u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */
+ os_atomic_t ah_ier_ref_count; /* reference count for enabling
interrupts */
+ struct ar9300_stats ah_stats; /* various statistics */
+ RF_HAL_FUNCS ah_rf_hal;
+ u_int32_t ah_tx_desc_mask; /* mask for TXDESC */
+ u_int32_t ah_tx_ok_interrupt_mask;
+ u_int32_t ah_tx_err_interrupt_mask;
+ u_int32_t ah_tx_desc_interrupt_mask;
+ u_int32_t ah_tx_eol_interrupt_mask;
+ u_int32_t ah_tx_urn_interrupt_mask;
+ HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
+ HAL_SMPS_MODE ah_sm_power_mode;
+ HAL_BOOL ah_chip_full_sleep;
+ u_int32_t ah_atim_window;
+ HAL_ANT_SETTING ah_diversity_control; /* antenna setting */
+ u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID
request */
+ u_int8_t ah_tx_chainmask_cfg; /* chain mask config */
+ u_int8_t ah_rx_chainmask_cfg;
+ u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */
+ /* Calibration related fields */
+ HAL_CAL_TYPES ah_supp_cals;
+ HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */
+ HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal
Data */
+ HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */
+ HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */
+ HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */
+// IQ Cal aliases
+#define ah_total_power_meas_i ah_meas0.unsign
+#define ah_total_power_meas_q ah_meas1.unsign
+#define ah_total_iq_corr_meas ah_meas2.sign
+ union {
+ u_int32_t unsign[AR9300_MAX_CHAINS];
+ int32_t sign[AR9300_MAX_CHAINS];
+ } ah_meas0;
+ union {
+ u_int32_t unsign[AR9300_MAX_CHAINS];
+ int32_t sign[AR9300_MAX_CHAINS];
+ } ah_meas1;
+ union {
+ u_int32_t unsign[AR9300_MAX_CHAINS];
+ int32_t sign[AR9300_MAX_CHAINS];
+ } ah_meas2;
+ union {
+ u_int32_t unsign[AR9300_MAX_CHAINS];
+ int32_t sign[AR9300_MAX_CHAINS];
+ } ah_meas3;
+ u_int16_t ah_cal_samples;
+ /* end - Calibration related fields */
+ u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */
+ u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */
+ u_int32_t ah_misc_mode; /* MISC_MODE settings */
+ HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */
+ enum {
+ AUTO_32KHZ, /* use it if 32kHz crystal present */
+ USE_32KHZ, /* do it regardless */
+ DONT_USE_32KHZ, /* don't use it regardless */
+ } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */
+
+ u_int32_t ah_ofdm_tx_power;
+ int16_t ah_tx_power_index_offset;
+
+ u_int ah_slot_time; /* user-specified slot time */
+ u_int ah_ack_timeout; /* user-specified ack timeout */
+ /*
+ * XXX
+ * 11g-specific stuff; belongs in the driver.
+ */
+ u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */
+ u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */
+ u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */
+ /*
+ * RF Silent handling; setup according to the EEPROM.
+ */
+ u_int32_t ah_gpio_select; /* GPIO pin to use */
+ u_int32_t ah_polarity; /* polarity to disable RF */
+ u_int32_t ah_gpio_bit; /* after init, prev value */
+ HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */
+
+#ifdef ATH_BT_COEX
+ /*
+ * Bluetooth coexistence static setup according to the registry
+ */
+ HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */
+ u_int8_t ah_bt_coex_config_type; /* BT coex configuration */
+ u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */
+ u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */
+ u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */
+ u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */
+ HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna
configuration */
+ u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in
dB */
+ /*
+ * Bluetooth coexistence runtime settings
+ */
+ HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is
enabled */
+ u_int32_t ah_bt_coex_mode; /* Register setting for
AR_BT_COEX_MODE */
+ u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register
setting for AR_BT_COEX_WEIGHT */
+ u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register
setting for AR_BT_COEX_WEIGHT */
+ u_int32_t ah_bt_coex_mode2; /* Register setting for
AR_BT_COEX_MODE2 */
+ u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex
*/
+#endif
+
+ /*
+ * Generic timer support
+ */
+ u_int32_t ah_avail_gen_timers; /* mask of available timers */
+ u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt
state */
+ u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt
state */
+ HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */
+
+ /*
+ * ANI & Radar support.
+ */
+ u_int32_t ah_proc_phy_err; /* Process Phy errs */
+ u_int32_t ah_ani_period; /* ani update list period */
+ struct ar9300_ani_state *ah_curani; /* cached last reference */
+ struct ar9300_ani_state ah_ani[255]; /* per-channel state */
+ struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel
Radar detector state */
+ struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */
+ struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write
state */
+ struct ar9300_ar_state ah_ar; /* AR detector state */
+ struct ar9300_radar_q_elem *ah_arq; /* AR event queue */
+ struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */
+
+ /*
+ * Transmit power state. Note these are maintained
+ * here so they can be retrieved by diagnostic tools.
+ */
+ u_int16_t ah_rates_array[16];
+
+ /*
+ * Tx queue interrupt state.
+ */
+ u_int32_t ah_intr_txqs;
+
+ HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */
+ HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */
+
+ /*
+ * Extension Channel Rx Clear State
+ */
+ u_int32_t ah_cycle_count;
+ u_int32_t ah_ctl_busy;
+ u_int32_t ah_ext_busy;
+
+ /* HT CWM state */
+ HAL_HT_EXTPROTSPACING ah_ext_prot_spacing;
+ u_int8_t ah_tx_chainmask; /* tx chain mask */
+ u_int8_t ah_rx_chainmask; /* rx chain mask */
+
+ u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */
+ u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */
+
+ int ah_hwp;
+ void *ah_cal_mem;
+ HAL_BOOL ah_emu_eeprom;
+
+ HAL_ANI_CMD ah_ani_function;
+ HAL_BOOL ah_rifs_enabled;
+ u_int32_t ah_rifs_reg[11];
+ u_int32_t ah_rifs_sec_cnt;
+
+ /* open-loop power control */
+ u_int32_t original_gain[22];
+ int32_t init_pdadc;
+ int32_t pdadc_delta;
+
+ /* cycle counts for beacon stuck diagnostics */
+ u_int32_t ah_cycles;
+ u_int32_t ah_rx_clear;
+ u_int32_t ah_rx_frame;
+ u_int32_t ah_tx_frame;
+
+#define BB_HANG_SIG1 0
+#define BB_HANG_SIG2 1
+#define BB_HANG_SIG3 2
+#define BB_HANG_SIG4 3
+#define MAC_HANG_SIG1 4
+#define MAC_HANG_SIG2 5
+ /* bb hang detection */
+ int ah_hang[6];
+ hal_hw_hangs_t ah_hang_wars;
+
+ /*
+ * Keytable type table
+ */
+#define AR_KEYTABLE_SIZE 128 /* XXX! */
+ uint8_t ah_keytype[AR_KEYTABLE_SIZE];
+#undef AR_KEYTABLE_SIZE
+ /*
+ * Support for ar9300 multiple INIs
+ */
+ struct ar9300_ini_array ah_ini_pcie_serdes;
+ struct ar9300_ini_array ah_ini_pcie_serdes_low_power;
+ struct ar9300_ini_array ah_ini_modes_additional;
+ struct ar9300_ini_array ah_ini_modes_additional_40mhz;
+ struct ar9300_ini_array ah_ini_modes_rxgain;
+ struct ar9300_ini_array ah_ini_modes_rxgain_bounds;
+ struct ar9300_ini_array ah_ini_modes_txgain;
+ struct ar9300_ini_array ah_ini_japan2484;
+ struct ar9300_ini_array ah_ini_radio_post_sys2ant;
+ struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR;
+ /*
+ * New INI format starting with Osprey 2.0 INI.
+ * Pre, core, post arrays for each sub-system (mac, bb, radio, soc)
+ */
+ #define ATH_INI_PRE 0
+ #define ATH_INI_CORE 1
+ #define ATH_INI_POST 2
+ #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1)
+ struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI
format */
+ struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI
format */
+ struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI
format */
+ struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI
format */
+
+ /*
+ * Added to support DFS postamble array in INI that we need to apply
+ * in DFS channels
+ */
+
+ struct ar9300_ini_array ah_ini_dfs;
+
+#if ATH_WOW
+ struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during
WOW sleep */
+#endif
+
+ /* To indicate EEPROM mapping used */
+ u_int32_t ah_immunity_vals[6];
+ HAL_BOOL ah_immunity_on;
+ /*
+ * snap shot of counter register for debug purposes
+ */
+#ifdef AH_DEBUG
+ u_int32_t last_tf;
+ u_int32_t last_rf;
+ u_int32_t last_rc;
+ u_int32_t last_cc;
+#endif
+ HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop.
*/
+ u_int32_t nf_tsf32; /* timestamp for NF calibration duration */
+
+ u_int32_t reg_dmn; /* Regulatory Domain */
+ int16_t twice_antenna_gain; /* Antenna Gain */
+ u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */
+
+ /*
+ * Upper limit after factoring in the regulatory max, antenna gain and
+ * multichain factor. No TxBF, CDD or STBC gain factored
+ */
+ int16_t upper_limit[AR9300_MAX_CHAINS];
+
+ /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */
+ int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
+
+ /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with
STBC*/
+ int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
+
+ /* Transmit Status ring support */
+ struct ar9300_txs *ts_ring;
+ u_int16_t ts_tail;
+ u_int16_t ts_size;
+ u_int32_t ts_paddr_start;
+ u_int32_t ts_paddr_end;
+
+ /* Receive Buffer size */
+#define HAL_RXBUFSIZE_DEFAULT 0xfff
+ u_int16_t rx_buf_size;
+
+ u_int32_t ah_wa_reg_val; // Store the permanent value of Reg
0x4004 so we dont have to R/M/W. (We should not be reading this register when
in sleep states).
+
+ /* Indicate the PLL source clock rate is 25Mhz or not.
+ * clk_25mhz = 0 by default.
+ */
+ u_int8_t clk_25mhz;
+ /* For PAPRD uses */
+ u_int16_t small_signal_gain[AH_MAX_CHAINS];
+ u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ];
+ u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ];
+ u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ];
+ u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of
eep->modal_header_2g.paprd_rate_mask_ht20 */
+ u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of
eep->modal_header_2g.paprd_rate_mask_ht40 */
+ u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of
eep->modal_header_5g.paprd_rate_mask_ht20 */
+ u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of
eep->modal_header_5g.paprd_rate_mask_ht40 */
+ u_int32_t paprd_training_power;
+ /* For GreenTx use to store the default tx power */
+ u_int8_t ah_default_tx_power[ar9300_rate_size];
+ HAL_BOOL ah_paprd_broken;
+
+ /* To store offsets of host interface registers */
+ struct {
+ u_int32_t AR_RC;
+ u_int32_t AR_WA;
+ u_int32_t AR_PM_STATE;
+ u_int32_t AR_H_INFOL;
+ u_int32_t AR_H_INFOH;
+ u_int32_t AR_PCIE_PM_CTRL;
+ u_int32_t AR_HOST_TIMEOUT;
+ u_int32_t AR_EEPROM;
+ u_int32_t AR_SREV;
+ u_int32_t AR_INTR_SYNC_CAUSE;
+ u_int32_t AR_INTR_SYNC_CAUSE_CLR;
+ u_int32_t AR_INTR_SYNC_ENABLE;
+ u_int32_t AR_INTR_ASYNC_MASK;
+ u_int32_t AR_INTR_SYNC_MASK;
+ u_int32_t AR_INTR_ASYNC_CAUSE_CLR;
+ u_int32_t AR_INTR_ASYNC_CAUSE;
+ u_int32_t AR_INTR_ASYNC_ENABLE;
+ u_int32_t AR_PCIE_SERDES;
+ u_int32_t AR_PCIE_SERDES2;
+ u_int32_t AR_GPIO_OUT;
+ u_int32_t AR_GPIO_IN;
+ u_int32_t AR_GPIO_OE_OUT;
+ u_int32_t AR_GPIO_OE1_OUT;
+ u_int32_t AR_GPIO_INTR_POL;
+ u_int32_t AR_GPIO_INPUT_EN_VAL;
+ u_int32_t AR_GPIO_INPUT_MUX1;
+ u_int32_t AR_GPIO_INPUT_MUX2;
+ u_int32_t AR_GPIO_OUTPUT_MUX1;
+ u_int32_t AR_GPIO_OUTPUT_MUX2;
+ u_int32_t AR_GPIO_OUTPUT_MUX3;
+ u_int32_t AR_INPUT_STATE;
+ u_int32_t AR_SPARE;
+ u_int32_t AR_PCIE_CORE_RESET_EN;
+ u_int32_t AR_CLKRUN;
+ u_int32_t AR_EEPROM_STATUS_DATA;
+ u_int32_t AR_OBS;
+ u_int32_t AR_RFSILENT;
+ u_int32_t AR_GPIO_PDPU;
+ u_int32_t AR_GPIO_DS;
+ u_int32_t AR_MISC;
+ u_int32_t AR_PCIE_MSI;
+ u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE;
+ u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY;
+ u_int32_t AR_TSF_SNAPSHOT_BT_CNTL;
+ u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ;
+ u_int32_t AR_TDMA_CCA_CNTL;
+ u_int32_t AR_TXAPSYNC;
+ u_int32_t AR_TXSYNC_INIT_SYNC_TMR;
+ u_int32_t AR_INTR_PRIO_SYNC_CAUSE;
+ u_int32_t AR_INTR_PRIO_SYNC_ENABLE;
+ u_int32_t AR_INTR_PRIO_ASYNC_MASK;
+ u_int32_t AR_INTR_PRIO_SYNC_MASK;
+ u_int32_t AR_INTR_PRIO_ASYNC_CAUSE;
+ u_int32_t AR_INTR_PRIO_ASYNC_ENABLE;
+ } ah_hostifregs;
+
+ u_int32_t ah_enterprise_mode;
+ u_int32_t ah_radar1;
+ u_int32_t ah_dc_offset;
+ HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */
+ HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */
+ u_int32_t ah_disable_cck;
+ HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */
+
+
+ /*
+ * Different types of memory where the calibration data might be stored.
+ * All types are searched in Ar9300EepromRestore() in the order flash,
eeprom, otp.
+ * To disable searching a type, set its parameter to 0.
+ */
+ int try_dram;
+ int try_flash;
+ int try_eeprom;
+ int try_otp;
+#ifdef ATH_CAL_NAND_FLASH
+ int try_nand;
+#endif
+ /*
+ * This is where we found the calibration data.
+ */
+ int calibration_data_source;
+ int calibration_data_source_address;
+ /*
+ * This is where we look for the calibration data. must be set before
ath_attach() is called
+ */
+ int calibration_data_try;
+ int calibration_data_try_address;
+ u_int8_t
+ tx_iq_cal_enable : 1,
+ tx_iq_cal_during_agc_cal : 1,
+ tx_cl_cal_enable : 1;
+
+#if ATH_SUPPORT_MCI
+ /* For MCI */
+ HAL_BOOL ah_mci_ready;
+ u_int32_t ah_mci_int_raw;
+ u_int32_t ah_mci_int_rx_msg;
+ u_int32_t ah_mci_rx_status;
+ u_int32_t ah_mci_cont_status;
+ u_int8_t ah_mci_bt_state;
+ u_int32_t ah_mci_gpm_addr;
+ u_int8_t *ah_mci_gpm_buf;
+ u_int32_t ah_mci_gpm_len;
+ u_int32_t ah_mci_gpm_idx;
+ u_int32_t ah_mci_sched_addr;
+ u_int8_t *ah_mci_sched_buf;
+ u_int8_t ah_mci_coex_major_version_wlan;
+ u_int8_t ah_mci_coex_minor_version_wlan;
+ u_int8_t ah_mci_coex_major_version_bt;
+ u_int8_t ah_mci_coex_minor_version_bt;
+ HAL_BOOL ah_mci_coex_bt_version_known;
+ HAL_BOOL ah_mci_coex_wlan_channels_update;
+ u_int32_t ah_mci_coex_wlan_channels[4];
+ HAL_BOOL ah_mci_coex_2g5g_update;
+ HAL_BOOL ah_mci_coex_is_2g;
+ HAL_BOOL ah_mci_query_bt;
+ HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */
+ HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */
+ HAL_BOOL ah_mci_need_flush_btinfo;
+ HAL_BOOL ah_mci_concur_tx_en;
+ u_int8_t ah_mci_stomp_low_tx_pri;
+ u_int8_t ah_mci_stomp_all_tx_pri;
+ u_int8_t ah_mci_stomp_none_tx_pri;
+ u_int32_t ah_mci_wlan_cal_seq;
+ u_int32_t ah_mci_wlan_cal_done;
+#if ATH_SUPPORT_AIC
+ HAL_BOOL ah_aic_enabled;
+ u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL];
+#endif
+#endif /* ATH_SUPPORT_MCI */
+ u_int8_t ah_cac_quiet_enabled;
+#if ATH_WOW_OFFLOAD
+ u_int32_t ah_mcast_filter_l32_set;
+ u_int32_t ah_mcast_filter_u32_set;
+#endif
+ HAL_BOOL ah_reduced_self_gen_mask;
+
+ /* Local additions for FreeBSD */
+ /*
+ * These fields are in the top level HAL in the atheros
+ * codebase; here we place them in the AR9300 HAL and
+ * access them via accessor methods if the driver requires them.
+ */
+ u_int32_t ah_ob_db1[3];
+ u_int32_t ah_db2[3];
+ u_int32_t ah_bb_panic_timeout_ms;
+ u_int32_t ah_bb_panic_last_status;
+ u_int32_t ah_tx_trig_level;
+ u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2];
+ int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW
interf threshold */
+ int ah_phyrestart_disabled;
+ HAL_RSSI_TX_POWER green_tx_status;
+ int green_ap_ps_on;
+ int ah_enable_keysearch_always;
+ int ah_fccaifs;
+ int ah_reset_reason;
+ int ah_dcs_enable;
+
+ struct ar9300NfLimits nf_2GHz;
+ struct ar9300NfLimits nf_5GHz;
+ struct ar9300NfLimits *nfp;
+
+};
+
+#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah))
+
+#define IS_9300_EMU(ah) \
+ (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE)
+
+#define ar9300_eep_data_in_flash(_ah) \
+ (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM))
+
+#ifdef notyet
+// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have
valid eeprom contents.
+&& \
+ ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <=
AR9300_EEP_MINOR_VER_16) || \
+ (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G))))
+#endif
+
+/*
+ * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows
+ * other cards' DMA reads to complete in the middle of our reset.
+ */
+#define WAR_6773(x) do { \
+ if ((++(x) % 64) == 0) \
+ OS_DELAY(1); \
+} while (0)
+
+#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
+ int r; \
+ for (r = 0; r < ((iniarray)->ia_rows); r++) { \
+ OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0),
INI_RA((iniarray), r, (column)));\
+ WAR_6773(regWr); \
+ } \
+} while (0)
+
+#define UPPER_5G_SUB_BANDSTART 5700
+#define MID_5G_SUB_BANDSTART 5400
+#define TRAINPOWER_DB_OFFSET 6
+
+#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G)
{ _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \
+ } else { \
+
if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale =
(_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \
+ else
if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \
+ {
_scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \
+ else {
_scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0)
+
+#ifdef AH_ASSERT
+ #define ar9300FeatureNotSupported(feature, ah, func) \
+ ath_hal_printf(ah, # feature \
+ " not supported but called from %s\n", (func)), \
+ hal_assert(0)
+#else
+ #define ar9300FeatureNotSupported(feature, ah, func) \
+ ath_hal_printf(ah, # feature \
+ " not supported but called from %s\n", (func))
+#endif /* AH_ASSERT */
+
+/*
+ * Green Tx, Based on different RSSI of Received Beacon thresholds,
+ * using different tx power by modified register tx power related values.
+ * The thresholds are decided by system team.
+ */
+#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */
+#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */
+#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta
+ Calibration Offset */
+#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value
+ in short distance*/
+#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value
+ in middle distance */
+#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value
+ in long distance */
+#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen
Tx
+ BB_powertx_rate9 reg
+ value in short
+ distance */
+#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen
Tx
+ BB_powertx_rate9 reg
+ value in middle
+ distance */
+
+
+/* Tx power for short distacnce in SwGreenTx.*/
+static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = {
+ 6, /*ALL_TARGET_LEGACY_6_24*/
+ 6, /*ALL_TARGET_LEGACY_36*/
+ 6, /*ALL_TARGET_LEGACY_48*/
+ 4, /*ALL_TARGET_LEGACY_54*/
+ 6, /*ALL_TARGET_LEGACY_1L_5L*/
+ 6, /*ALL_TARGET_LEGACY_5S*/
+ 6, /*ALL_TARGET_LEGACY_11L*/
+ 6, /*ALL_TARGET_LEGACY_11S*/
+ 6, /*ALL_TARGET_HT20_0_8_16*/
+ 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
+ 4, /*ALL_TARGET_HT20_4*/
+ 4, /*ALL_TARGET_HT20_5*/
+ 4, /*ALL_TARGET_HT20_6*/
+ 2, /*ALL_TARGET_HT20_7*/
+ 0, /*ALL_TARGET_HT20_12*/
+ 0, /*ALL_TARGET_HT20_13*/
+ 0, /*ALL_TARGET_HT20_14*/
+ 0, /*ALL_TARGET_HT20_15*/
+ 0, /*ALL_TARGET_HT20_20*/
+ 0, /*ALL_TARGET_HT20_21*/
+ 0, /*ALL_TARGET_HT20_22*/
+ 0, /*ALL_TARGET_HT20_23*/
+ 6, /*ALL_TARGET_HT40_0_8_16*/
+ 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
+ 4, /*ALL_TARGET_HT40_4*/
+ 4, /*ALL_TARGET_HT40_5*/
+ 4, /*ALL_TARGET_HT40_6*/
+ 2, /*ALL_TARGET_HT40_7*/
+ 0, /*ALL_TARGET_HT40_12*/
+ 0, /*ALL_TARGET_HT40_13*/
+ 0, /*ALL_TARGET_HT40_14*/
+ 0, /*ALL_TARGET_HT40_15*/
+ 0, /*ALL_TARGET_HT40_20*/
+ 0, /*ALL_TARGET_HT40_21*/
+ 0, /*ALL_TARGET_HT40_22*/
+ 0 /*ALL_TARGET_HT40_23*/
+};
+
+/* Tx power for middle distacnce in SwGreenTx.*/
+static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = {
+ 14, /*ALL_TARGET_LEGACY_6_24*/
+ 14, /*ALL_TARGET_LEGACY_36*/
+ 14, /*ALL_TARGET_LEGACY_48*/
+ 12, /*ALL_TARGET_LEGACY_54*/
+ 14, /*ALL_TARGET_LEGACY_1L_5L*/
+ 14, /*ALL_TARGET_LEGACY_5S*/
+ 14, /*ALL_TARGET_LEGACY_11L*/
+ 14, /*ALL_TARGET_LEGACY_11S*/
+ 14, /*ALL_TARGET_HT20_0_8_16*/
+ 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
+ 14, /*ALL_TARGET_HT20_4*/
+ 14, /*ALL_TARGET_HT20_5*/
+ 12, /*ALL_TARGET_HT20_6*/
+ 10, /*ALL_TARGET_HT20_7*/
+ 0, /*ALL_TARGET_HT20_12*/
+ 0, /*ALL_TARGET_HT20_13*/
+ 0, /*ALL_TARGET_HT20_14*/
+ 0, /*ALL_TARGET_HT20_15*/
+ 0, /*ALL_TARGET_HT20_20*/
+ 0, /*ALL_TARGET_HT20_21*/
+ 0, /*ALL_TARGET_HT20_22*/
+ 0, /*ALL_TARGET_HT20_23*/
+ 14, /*ALL_TARGET_HT40_0_8_16*/
+ 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
+ 14, /*ALL_TARGET_HT40_4*/
+ 14, /*ALL_TARGET_HT40_5*/
+ 12, /*ALL_TARGET_HT40_6*/
+ 10, /*ALL_TARGET_HT40_7*/
+ 0, /*ALL_TARGET_HT40_12*/
+ 0, /*ALL_TARGET_HT40_13*/
+ 0, /*ALL_TARGET_HT40_14*/
+ 0, /*ALL_TARGET_HT40_15*/
+ 0, /*ALL_TARGET_HT40_20*/
+ 0, /*ALL_TARGET_HT40_21*/
+ 0, /*ALL_TARGET_HT40_22*/
+ 0 /*ALL_TARGET_HT40_23*/
+};
+
+/* OLPC DeltaCalibration Offset unit in half dB.*/
+static const u_int8_t wb225_gtx_olpc_cal_offset[6] = {
+ 0, /* OB0*/
+ 16, /* OB1*/
+ 9, /* OB2*/
+ 5, /* OB3*/
+ 2, /* OB4*/
+ 0, /* OB5*/
+};
+
+/*
+ * Definitions for HwGreenTx
+ */
+#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */
+#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */
+#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen
Tx
+ BB_powertx_rate9 reg
+ value in short
+ distance */
+#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For
HwGreenTx
+ BB_powertx_rate9 reg
+ value in middle
+ distance */
+
+/* Tx power for short distacnce in HwGreenTx.*/
+static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = {
+ 14, /*ALL_TARGET_LEGACY_6_24*/
+ 14, /*ALL_TARGET_LEGACY_36*/
+ 8, /*ALL_TARGET_LEGACY_48*/
+ 2, /*ALL_TARGET_LEGACY_54*/
+ 14, /*ALL_TARGET_LEGACY_1L_5L*/
+ 14, /*ALL_TARGET_LEGACY_5S*/
+ 14, /*ALL_TARGET_LEGACY_11L*/
+ 14, /*ALL_TARGET_LEGACY_11S*/
+ 12, /*ALL_TARGET_HT20_0_8_16*/
+ 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
+ 12, /*ALL_TARGET_HT20_4*/
+ 12, /*ALL_TARGET_HT20_5*/
+ 8, /*ALL_TARGET_HT20_6*/
+ 2, /*ALL_TARGET_HT20_7*/
+ 0, /*ALL_TARGET_HT20_12*/
+ 0, /*ALL_TARGET_HT20_13*/
+ 0, /*ALL_TARGET_HT20_14*/
+ 0, /*ALL_TARGET_HT20_15*/
+ 0, /*ALL_TARGET_HT20_20*/
+ 0, /*ALL_TARGET_HT20_21*/
+ 0, /*ALL_TARGET_HT20_22*/
+ 0, /*ALL_TARGET_HT20_23*/
+ 10, /*ALL_TARGET_HT40_0_8_16*/
+ 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
+ 10, /*ALL_TARGET_HT40_4*/
+ 10, /*ALL_TARGET_HT40_5*/
+ 6, /*ALL_TARGET_HT40_6*/
+ 2, /*ALL_TARGET_HT40_7*/
+ 0, /*ALL_TARGET_HT40_12*/
+ 0, /*ALL_TARGET_HT40_13*/
+ 0, /*ALL_TARGET_HT40_14*/
+ 0, /*ALL_TARGET_HT40_15*/
+ 0, /*ALL_TARGET_HT40_20*/
+ 0, /*ALL_TARGET_HT40_21*/
+ 0, /*ALL_TARGET_HT40_22*/
+ 0 /*ALL_TARGET_HT40_23*/
+};
+
+/* Tx power for middle distacnce in HwGreenTx.*/
+static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = {
+ 18, /*ALL_TARGET_LEGACY_6_24*/
+ 18, /*ALL_TARGET_LEGACY_36*/
+ 14, /*ALL_TARGET_LEGACY_48*/
+ 12, /*ALL_TARGET_LEGACY_54*/
+ 18, /*ALL_TARGET_LEGACY_1L_5L*/
+ 18, /*ALL_TARGET_LEGACY_5S*/
+ 18, /*ALL_TARGET_LEGACY_11L*/
+ 18, /*ALL_TARGET_LEGACY_11S*/
+ 16, /*ALL_TARGET_HT20_0_8_16*/
+ 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
+ 16, /*ALL_TARGET_HT20_4*/
+ 16, /*ALL_TARGET_HT20_5*/
+ 14, /*ALL_TARGET_HT20_6*/
+ 12, /*ALL_TARGET_HT20_7*/
+ 0, /*ALL_TARGET_HT20_12*/
+ 0, /*ALL_TARGET_HT20_13*/
+ 0, /*ALL_TARGET_HT20_14*/
+ 0, /*ALL_TARGET_HT20_15*/
+ 0, /*ALL_TARGET_HT20_20*/
+ 0, /*ALL_TARGET_HT20_21*/
+ 0, /*ALL_TARGET_HT20_22*/
+ 0, /*ALL_TARGET_HT20_23*/
+ 14, /*ALL_TARGET_HT40_0_8_16*/
+ 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
+ 14, /*ALL_TARGET_HT40_4*/
+ 14, /*ALL_TARGET_HT40_5*/
+ 14, /*ALL_TARGET_HT40_6*/
[ *** diff truncated: 247721 lines dropped *** ]
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