[haiku-commits] haiku: hrev44169 - headers/private/kernel/arch/arm src/system/kernel/arch/arm headers/private/kernel/arch/generic
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Thu, 17 May 2012 16:24:35 +0200 (CEST)
hrev44169 adds 2 changesets to branch 'master'
old head: e9ec7a55ddffa7a4f12eb8d425f43ec10c5ab258
new head: eb93f2661d536dcb074a0a4e49842227e3023427
----------------------------------------------------------------------------
182643f: uart: Remove due to mmu's new (better) UART code
eb93f26: uart: Style Cleanup, no functional change
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
9 files changed, 48 insertions(+), 662 deletions(-)
headers/private/kernel/arch/arm/arch_uart_pl011.h | 26 +-
headers/private/kernel/arch/arm/uart_8250.h | 58 -----
headers/private/kernel/arch/arm/uart_pl011.h | 173 -------------
headers/private/kernel/arch/generic/debug_uart.h | 39 +--
.../private/kernel/arch/generic/debug_uart_8250.h | 18 +-
src/system/kernel/arch/arm/arch_uart_8250.cpp | 4 +-
src/system/kernel/arch/arm/arch_uart_pl011.cpp | 2 -
src/system/kernel/arch/arm/uart_8250.cpp | 207 ----------------
src/system/kernel/arch/arm/uart_pl011.cpp | 183 --------------
############################################################################
Commit: 182643f76394a7d3e1e2d8664bae681e7965bfa5
URL: http://cgit.haiku-os.org/haiku/commit/?id=182643f
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Thu May 17 08:14:31 2012 UTC
uart: Remove due to mmu's new (better) UART code
----------------------------------------------------------------------------
diff --git a/headers/private/kernel/arch/arm/uart_8250.h
b/headers/private/kernel/arch/arm/uart_8250.h
deleted file mode 100644
index 137d5d1..0000000
--- a/headers/private/kernel/arch/arm/uart_8250.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2008 Travis Geiselbrecht
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files
- * (the "Software"), to deal in the Software without restriction,
- * including without limitation the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef __DEV_UART_8250_H
-#define __DEV_UART_8250_H
-
-
-#include <SupportDefs.h>
-#include <sys/types.h>
-
-
-class Uart8250 {
-public:
- Uart8250(addr_t base);
- ~Uart8250();
-
- void InitEarly();
- void Init();
- void InitPort(uint32 baud);
-
- void Enable();
- void Disable();
-
- int PutChar(char c);
- int GetChar(bool wait);
-
- void FlushTx();
- void FlushRx();
-
-private:
- void WriteUart(uint32 reg, unsigned
char data);
- unsigned char ReadUart(uint32 reg);
-
- bool fUARTEnabled;
- addr_t fUARTBase;
-};
-
-
-#endif
diff --git a/headers/private/kernel/arch/arm/uart_pl011.h
b/headers/private/kernel/arch/arm/uart_pl011.h
deleted file mode 100644
index 79d9c8c..0000000
--- a/headers/private/kernel/arch/arm/uart_pl011.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2011-2012 Haiku, Inc. All rights reserved.
- * Distributed under the terms of the MIT License.
- *
- * Authors:
- * Alexander von Gluck, kallisti5@xxxxxxxxxxx
- */
-#ifndef __DEV_UART_PL011_H
-#define __DEV_UART_PL011_H
-
-
-#include <sys/types.h>
-#include <SupportDefs.h>
-
-
-#define PL01x_DR 0x00 // Data read or written
-#define PL01x_RSR 0x04 // Receive status, read
-#define PL01x_ECR 0x04 // Error clear, write
-#define PL010_LCRH 0x08 // Line control, high
-#define PL010_LCRM 0x0C // Line control, middle
-#define PL010_LCRL 0x10 // Line control, low
-#define PL010_CR 0x14 // Control
-#define PL01x_FR 0x18 // Flag (r/o)
-#define PL010_IIR 0x1C // Interrupt ID (r)
-#define PL010_ICR 0x1C // Interrupt clear (w)
-#define PL01x_ILPR 0x20 // IrDA low power
-#define PL011_IBRD 0x24 // Interrupt baud rate divisor
-#define PL011_FBRD 0x28 // Fractional baud rate divisor
-#define PL011_LCRH 0x2C // Line control
-#define PL011_CR 0x30 // Control
-#define PL011_IFLS 0x34 // Interrupt fifo level
-#define PL011_IMSC 0x38 // Interrupt mask
-#define PL011_RIS 0x3C // Raw interrupt
-#define PL011_MIS 0x40 // Masked interrupt
-#define PL011_ICR 0x44 // Interrupt clear
-#define PL011_DMACR 0x48 // DMA control register
-
-#define PL011_DR_OE (1 << 11)
-#define PL011_DR_BE (1 << 10)
-#define PL011_DR_PE (1 << 9)
-#define PL011_DR_FE (1 << 8)
-
-#define PL01x_RSR_OE 0x08
-#define PL01x_RSR_BE 0x04
-#define PL01x_RSR_PE 0x02
-#define PL01x_RSR_FE 0x01
-
-#define PL011_FR_RI 0x100
-#define PL011_FR_TXFE 0x080
-#define PL011_FR_RXFF 0x040
-#define PL01x_FR_TXFF 0x020
-#define PL01x_FR_RXFE 0x010
-#define PL01x_FR_BUSY 0x008
-#define PL01x_FR_DCD 0x004
-#define PL01x_FR_DSR 0x002
-#define PL01x_FR_CTS 0x001
-#define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY)
-
-#define PL011_CR_CTSEN 0x8000 // CTS flow control
-#define PL011_CR_RTSEN 0x4000 // RTS flow control
-#define PL011_CR_OUT2 0x2000 // OUT2
-#define PL011_CR_OUT1 0x1000 // OUT1
-#define PL011_CR_RTS 0x0800 // RTS
-#define PL011_CR_DTR 0x0400 // DTR
-#define PL011_CR_RXE 0x0200 // Receive enable
-#define PL011_CR_TXE 0x0100 // Transmit enable
-#define PL011_CR_LBE 0x0080 // Loopback enable
-#define PL010_CR_RTIE 0x0040
-#define PL010_CR_TIE 0x0020
-#define PL010_CR_RIE 0x0010
-#define PL010_CR_MSIE 0x0008
-#define PL01x_CR_IIRLP 0x0004 // SIR low power mode
-#define PL01x_CR_SIREN 0x0002 // SIR enable
-#define PL01x_CR_UARTEN 0x0001 // UART enable
-
-#define PL011_LCRH_SPS 0x80
-#define PL01x_LCRH_WLEN_8 0x60
-#define PL01x_LCRH_WLEN_7 0x40
-#define PL01x_LCRH_WLEN_6 0x20
-#define PL01x_LCRH_WLEN_5 0x00
-#define PL01x_LCRH_FEN 0x10
-#define PL01x_LCRH_STP2 0x08
-#define PL01x_LCRH_EPS 0x04
-#define PL01x_LCRH_PEN 0x02
-#define PL01x_LCRH_BRK 0x01
-
-#define PL010_IIR_RTIS 0x08
-#define PL010_IIR_TIS 0x04
-#define PL010_IIR_RIS 0x02
-#define PL010_IIR_MIS 0x01
-
-#define PL011_IFLS_RX1_8 (0 << 3)
-#define PL011_IFLS_RX2_8 (1 << 3)
-#define PL011_IFLS_RX4_8 (2 << 3)
-#define PL011_IFLS_RX6_8 (3 << 3)
-#define PL011_IFLS_RX7_8 (4 << 3)
-#define PL011_IFLS_TX1_8 (0 << 0)
-#define PL011_IFLS_TX2_8 (1 << 0)
-#define PL011_IFLS_TX4_8 (2 << 0)
-#define PL011_IFLS_TX6_8 (3 << 0)
-#define PL011_IFLS_TX7_8 (4 << 0)
-
-#define PL011_IFLS_RX_HALF (5 << 3) // ST vendor only
-#define PL011_IFLS_TX_HALF (5 << 0) // ST vendor only
-
-#define PL011_OEIM (1 << 10) // overrun error interrupt mask
-#define PL011_BEIM (1 << 9) // break error interrupt mask
-#define PL011_PEIM (1 << 8) // parity error interrupt mask
-#define PL011_FEIM (1 << 7) // framing error interrupt mask
-#define PL011_RTIM (1 << 6) // receive timeout interrupt mask
-#define PL011_TXIM (1 << 5) // transmit interrupt mask
-#define PL011_RXIM (1 << 4) // receive interrupt mask
-#define PL011_DSRMIM (1 << 3) // DSR interrupt mask
-#define PL011_DCDMIM (1 << 2) // DCD interrupt mask
-#define PL011_CTSMIM (1 << 1) // CTS interrupt mask
-#define PL011_RIMIM (1 << 0) // RI interrupt mask
-
-#define PL011_OEIS (1 << 10) // overrun error interrupt state
-#define PL011_BEIS (1 << 9) // break error interrupt state
-#define PL011_PEIS (1 << 8) // parity error interrupt state
-#define PL011_FEIS (1 << 7) // framing error interrupt state
-#define PL011_RTIS (1 << 6) // receive timeout interrupt state
-#define PL011_TXIS (1 << 5) // transmit interrupt state
-#define PL011_RXIS (1 << 4) // receive interrupt state
-#define PL011_DSRMIS (1 << 3) // DSR interrupt state
-#define PL011_DCDMIS (1 << 2) // DCD interrupt state
-#define PL011_CTSMIS (1 << 1) // CTS interrupt state
-#define PL011_RIMIS (1 << 0) // RI interrupt state
-
-#define PL011_OEIC (1 << 10) // overrun error interrupt clear
-#define PL011_BEIC (1 << 9) // break error interrupt clear
-#define PL011_PEIC (1 << 8) // parity error interrupt clear
-#define PL011_FEIC (1 << 7) // framing error interrupt clear
-#define PL011_RTIC (1 << 6) // receive timeout interrupt clear
-#define PL011_TXIC (1 << 5) // transmit interrupt clear
-#define PL011_RXIC (1 << 4) // receive interrupt clear
-#define PL011_DSRMIC (1 << 3) // DSR interrupt clear
-#define PL011_DCDMIC (1 << 2) // DCD interrupt clear
-#define PL011_CTSMIC (1 << 1) // CTS interrupt clear
-#define PL011_RIMIC (1 << 0) // RI interrupt clear
-
-#define PL011_DMAONERR (1 << 2) // disable dma on err
-#define PL011_TXDMAE (1 << 1) // enable transmit dma
-#define PL011_RXDMAE (1 << 0) // enable receive dma
-
-
-class UartPL011 {
-public:
- UartPL011(addr_t base);
- ~UartPL011();
-
- void InitEarly();
- void InitPort(uint32 baud);
-
- void Enable();
- void Disable();
-
- int PutChar(char c);
- int GetChar(bool wait);
-
- void FlushTx();
- void FlushRx();
-
-private:
- void WriteUart(uint32 reg, uint32
data);
- uint32 ReadUart(uint32 reg);
-
- bool fUARTEnabled;
- addr_t fUARTBase;
-};
-
-
-#endif
diff --git a/src/system/kernel/arch/arm/uart_8250.cpp
b/src/system/kernel/arch/arm/uart_8250.cpp
deleted file mode 100644
index f8c3dcb..0000000
--- a/src/system/kernel/arch/arm/uart_8250.cpp
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (c) 2008 Travis Geiselbrecht
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files
- * (the "Software"), to deal in the Software without restriction,
- * including without limitation the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-#include <debug.h>
-#include <arch/arm/reg.h>
-#include <arch/arm/uart.h>
-#include <board_config.h>
-//#include <target/debugconfig.h>
-
-
-#define UART_SHIFT 2
-
-
-Uart8250::Uart8250(addr_t base)
- :
- fUARTEnabled(true),
- fUARTBase(base)
-{
-}
-
-
-Uart8250::~Uart8250()
-{
-}
-
-
-void
-Uart8250::WriteUart(uint32 reg, unsigned char data)
-{
- *(volatile unsigned char *)(fUARTBase + (reg << UART_SHIFT))
- = data;
-}
-
-
-unsigned char
-Uart8250::ReadUart(uint32 reg)
-{
- return *(volatile unsigned char *)(fUARTBase + (reg << UART_SHIFT));
-}
-
-
-#define LCR_8N1 0x03
-
-#define FCR_FIFO_EN 0x01 /* Fifo enable */
-#define FCR_RXSR 0x02 /* Receiver soft reset */
-#define FCR_TXSR 0x04 /* Transmitter soft reset */
-
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DMA_EN 0x04
-#define MCR_TX_DFR 0x08
-
-#define LCR_WLS_MSK 0x03 /* character length select mask */
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on =
1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble */
-#define LCR_EPS 0x10 /* Even Parity Select */
-#define LCR_STKP 0x20 /* Stick Parity */
-#define LCR_SBRK 0x40 /* Set Break */
-#define LCR_BKSE 0x80 /* Bank select enable */
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-
-void
-Uart8250::InitPort(uint32 baud)
-{
- Disable();
-
- uint16 baudDivisor = BOARD_UART_CLOCK / (16 * baud);
-
- // Write standard uart settings
- WriteUart(UART_LCR, LCR_8N1);
- // 8N1
- WriteUart(UART_IER, 0);
- // Disable interrupt
- WriteUart(UART_FCR, 0);
- // Disable FIFO
- WriteUart(UART_MCR, MCR_DTR | MCR_RTS);
- // DTR / RTS
-
- // Gain access to, and program baud divisor
- unsigned char buffer = ReadUart(UART_LCR);
- WriteUart(UART_LCR, buffer | LCR_BKSE);
- WriteUart(UART_DLL, baudDivisor & 0xff);
- WriteUart(UART_DLH, (baudDivisor >> 8) & 0xff);
- WriteUart(UART_LCR, buffer & ~LCR_BKSE);
-
-// WriteUart(UART_MDR1, 0); // UART 16x mode
-// WriteUart(UART_LCR, 0xBF); // config mode B
-// WriteUart(UART_EFR, (1<<7)|(1<<6)); // hw flow control
-// WriteUart(UART_LCR, LCR_8N1); // operational mode
-
- Enable();
-}
-
-
-void
-Uart8250::InitEarly()
-{
- // Perform special hardware UART configuration
-
- #if BOARD_CPU_OMAP3
- /* UART1 */
- RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1);
- RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1);
-
- /* UART2 */
- RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1);
- RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1);
-
- /* UART3 */
- RMWREG32(CM_FCLKEN_PER, 11, 1, 1);
- RMWREG32(CM_ICLKEN_PER, 11, 1, 1);
- #else
- #warning INTITIALIZE UART!!!!!
- #endif
-}
-
-
-void
-Uart8250::Enable()
-{
- fUARTEnabled = true;
-}
-
-
-void
-Uart8250::Disable()
-{
- fUARTEnabled = false;
-}
-
-
-int
-Uart8250::PutChar(char c)
-{
- while (!(ReadUart(UART_LSR) & (1<<6)));
- // wait for the last char to get out
- WriteUart(UART_THR, c);
- return 0;
-}
-
-
-/* returns -1 if no data available */
-int
-Uart8250::GetChar(bool wait)
-{
- if (wait) {
- while (!(ReadUart(UART_LSR) & (1<<0)));
- // wait for data to show up in the rx fifo
- } else {
- if (!(ReadUart(UART_LSR) & (1<<0)))
- return -1;
- }
- return ReadUart(UART_RHR);
-}
-
-
-void
-Uart8250::FlushTx()
-{
- while (!(ReadUart(UART_LSR) & (1<<6)));
- // wait for the last char to get out
-}
-
-
-void
-Uart8250::FlushRx()
-{
- // empty the rx fifo
- while (ReadUart(UART_LSR) & (1<<0)) {
- volatile char c = ReadUart(UART_RHR);
- (void)c;
- }
-}
diff --git a/src/system/kernel/arch/arm/uart_pl011.cpp
b/src/system/kernel/arch/arm/uart_pl011.cpp
deleted file mode 100644
index 9c05d41..0000000
--- a/src/system/kernel/arch/arm/uart_pl011.cpp
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright 2011-2012 Haiku, Inc. All rights reserved.
- * Distributed under the terms of the MIT License.
- *
- * Authors:
- * Alexander von Gluck, kallisti5@xxxxxxxxxxx
- */
-
-
-#include <debug.h>
-#include <arch/arm/reg.h>
-#include <arch/arm/uart.h>
-#include <board_config.h>
-//#include <target/debugconfig.h>
-
-
-static void
-barrier()
-{
- asm volatile ("" : : : "memory");
-}
-
-
-UartPL011::UartPL011(addr_t base)
- :
- fUARTEnabled(true),
- fUARTBase(base)
-{
- barrier();
-
- // ** Loopback test
- uint32 cr = PL01x_CR_UARTEN;
- // Enable UART
- cr |= PL011_CR_TXE;
- // Enable TX
- cr |= PL011_CR_LBE;
- // Enable Loopback mode
- WriteUart(PL011_CR, cr);
-
- WriteUart(PL011_FBRD, 0);
- WriteUart(PL011_IBRD, 1);
- WriteUart(PL011_LCRH, 0); // TODO: ST is different tx, rx lcr
-
- // Write a 0 to the port and wait for confim..
- WriteUart(PL01x_DR, 0);
-
- while (ReadUart(PL01x_FR) & PL01x_FR_BUSY)
- barrier();
-
- // ** Disable loopback, enable uart
- cr = PL01x_CR_UARTEN | PL011_CR_RXE | PL011_CR_TXE;
- WriteUart(PL011_CR, cr);
-
- // ** Clear interrupts
- WriteUart(PL011_ICR, PL011_OEIS | PL011_BEIS
- | PL011_PEIS | PL011_FEIS);
-
- // ** Disable interrupts
- WriteUart(PL011_IMSC, 0);
-}
-
-
-UartPL011::~UartPL011()
-{
-}
-
-
-void
-UartPL011::WriteUart(uint32 reg, uint32 data)
-{
- *(volatile uint32*)(fUARTBase + reg) = data;
-}
-
-
-uint32
-UartPL011::ReadUart(uint32 reg)
-{
- return *(volatile uint32*)(fUARTBase + reg);
-}
-
-
-void
-UartPL011::InitPort(uint32 baud)
-{
- // Calculate baud divisor
- uint32 baudDivisor = BOARD_UART_CLOCK / (16 * baud);
- uint32 remainder = BOARD_UART_CLOCK % (16 * baud);
- uint32 baudFractional = ((8 * remainder) / baud >> 1)
- + ((8 * remainder) / baud & 1);
-
- // Disable UART
- Disable();
-
- // Set baud divisor
- WriteUart(PL011_IBRD, baudDivisor);
- WriteUart(PL011_FBRD, baudFractional);
-
- // Set LCR 8n1, enable fifo
- WriteUart(PL011_LCRH, PL01x_LCRH_WLEN_8 | PL01x_LCRH_FEN);
-
- // Enable UART
- Enable();
-}
-
-
-void
-UartPL011::InitEarly()
-{
- // Perform special hardware UART configuration
-}
-
-
-void
-UartPL011::Enable()
-{
- uint32 cr = PL01x_CR_UARTEN;
- // Enable UART
- cr |= PL011_CR_TXE | PL011_CR_RXE;
- // Enable TX and RX
-
- WriteUart(PL011_CR, cr);
-
- fUARTEnabled = true;
-}
-
-
-void
-UartPL011::Disable()
-{
- // Disable everything
- WriteUart(PL011_CR, 0);
- fUARTEnabled = false;
-}
-
-
-int
-UartPL011::PutChar(char c)
-{
- if (fUARTEnabled == true) {
- // Wait until there is room in fifo
- while ((ReadUart(PL01x_FR) & PL01x_FR_TXFF) != 0)
- barrier();
-
- WriteUart(PL01x_DR, c);
- return 0;
- }
-
- return -1;
-}
-
-
-int
-UartPL011::GetChar(bool wait)
-{
- if (fUARTEnabled == true) {
- // Wait until a character is received?
- if (wait) {
- while ((ReadUart(PL01x_FR) & PL01x_FR_RXFE) != 0)
- barrier();
- }
- return ReadUart(PL01x_DR);
- }
-
- return -1;
-}
-
-
-void
-UartPL011::FlushTx()
-{
- // Wait until transmit fifo empty
- while ((ReadUart(PL01x_FR) & PL011_FR_TXFE) == 0)
- barrier();
-}
-
-
-void
-UartPL011::FlushRx()
-{
- // Wait until receive fifo empty
- while ((ReadUart(PL01x_FR) & PL01x_FR_RXFE) == 0)
- barrier();
-}
############################################################################
Revision: hrev44169
Commit: eb93f2661d536dcb074a0a4e49842227e3023427
URL: http://cgit.haiku-os.org/haiku/commit/?id=eb93f26
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Thu May 17 08:31:02 2012 UTC
uart: Style Cleanup, no functional change
----------------------------------------------------------------------------
diff --git a/headers/private/kernel/arch/arm/arch_uart_pl011.h
b/headers/private/kernel/arch/arm/arch_uart_pl011.h
index 19a25e2..de335ba 100644
--- a/headers/private/kernel/arch/arm/arch_uart_pl011.h
+++ b/headers/private/kernel/arch/arm/arch_uart_pl011.h
@@ -10,33 +10,37 @@
#include <sys/types.h>
+
#include <SupportDefs.h>
+
#include <arch/generic/debug_uart.h>
+
class ArchUARTPL011 : public DebugUART {
public:
ArchUARTPL011(addr_t
base, int64 clock);
~ArchUARTPL011();
- void InitEarly();
- void InitPort(uint32 baud);
+ void InitEarly();
+ void InitPort(uint32 baud);
- void Enable();
- void Disable();
+ void Enable();
+ void Disable();
- int PutChar(char c);
- int GetChar(bool wait);
+ int PutChar(char c);
+ int GetChar(bool wait);
- void FlushTx();
- void FlushRx();
+ void FlushTx();
+ void FlushRx();
private:
- void Out32(int reg, uint32 value);
- uint32 In32(int reg);
- virtual void Barrier();
+ void Out32(int reg, uint32 value);
+ uint32 In32(int reg);
+ virtual void Barrier();
};
ArchUARTPL011 *arch_get_uart_pl011(addr_t base, int64 clock);
+
#endif
diff --git a/headers/private/kernel/arch/generic/debug_uart.h
b/headers/private/kernel/arch/generic/debug_uart.h
index 4a2cf03..3d2fae7 100644
--- a/headers/private/kernel/arch/generic/debug_uart.h
+++ b/headers/private/kernel/arch/generic/debug_uart.h
@@ -9,9 +9,10 @@
#define _KERNEL_ARCH_DEBUG_UART_H
-#include <SupportDefs.h>
#include <sys/types.h>
+#include <SupportDefs.h>
+
class DebugUART {
public:
@@ -21,35 +22,35 @@ public:
fEnabled(true)
{};
~DebugUART() {};
- virtual void InitEarly() {};
- virtual void Init() {};
- virtual void InitPort(uint32 baud) {};
+ virtual void InitEarly() {};
+ virtual void Init() {};
+ virtual void InitPort(uint32 baud) {};
- virtual void Enable() { fEnabled = true; }
- virtual void Disable() { fEnabled = false; }
+ virtual void Enable() { fEnabled = true; }
+ virtual void Disable() { fEnabled = false; }
- virtual int PutChar(char c) = 0;
- virtual int GetChar(bool wait) = 0;
+ virtual int PutChar(char c) = 0;
+ virtual int GetChar(bool wait) = 0;
- virtual void FlushTx() = 0;
- virtual void FlushRx() = 0;
+ virtual void FlushTx() = 0;
+ virtual void FlushRx() = 0;
- addr_t Base() const { return fBase; }
- int64 Clock() const { return fClock; }
- bool Enabled() const { return
fEnabled; }
+ addr_t Base() const { return fBase; }
+ int64 Clock() const { return fClock; }
+ bool Enabled() const { return
fEnabled; }
protected:
// default MMIO
- virtual void Out8(int reg, uint8 value)
+ virtual void Out8(int reg, uint8 value)
{ *((uint8
*)Base() + reg) = value; }
- virtual uint8 In8(int reg)
+ virtual uint8 In8(int reg)
{ return
*((uint8 *)Base() + reg); }
- virtual void Barrier() {}
+ virtual void Barrier() {}
private:
- addr_t fBase;
- int64 fClock;
- bool fEnabled;
+ addr_t fBase;
+ int64 fClock;
+ bool fEnabled;
};
diff --git a/headers/private/kernel/arch/generic/debug_uart_8250.h
b/headers/private/kernel/arch/generic/debug_uart_8250.h
index d4887c9..e7f211f 100644
--- a/headers/private/kernel/arch/generic/debug_uart_8250.h
+++ b/headers/private/kernel/arch/generic/debug_uart_8250.h
@@ -9,9 +9,10 @@
#define _KERNEL_ARCH_DEBUG_UART_8250_H
-#include <SupportDefs.h>
#include <sys/types.h>
+#include <SupportDefs.h>
+
#include "debug_uart.h"
@@ -20,18 +21,19 @@ public:
DebugUART8250(addr_t
base, int64 clock);
~DebugUART8250();
- void InitEarly();
- void Init();
- void InitPort(uint32 baud);
+ void InitEarly();
+ void Init();
+ void InitPort(uint32 baud);
- int PutChar(char c);
- int GetChar(bool wait);
+ int PutChar(char c);
+ int GetChar(bool wait);
- void FlushTx();
- void FlushRx();
+ void FlushTx();
+ void FlushRx();
};
extern DebugUART8250 *arch_get_uart_8250(addr_t base, int64 clock);
+
#endif /* _KERNEL_ARCH_DEBUG_UART_8250_H */
diff --git a/src/system/kernel/arch/arm/arch_uart_8250.cpp
b/src/system/kernel/arch/arm/arch_uart_8250.cpp
index 94d07d3..6e91e6f 100644
--- a/src/system/kernel/arch/arm/arch_uart_8250.cpp
+++ b/src/system/kernel/arch/arm/arch_uart_8250.cpp
@@ -34,6 +34,7 @@ ArchUART8250::~ArchUART8250()
{
}
+
void
ArchUART8250::InitEarly()
{
@@ -55,6 +56,8 @@ ArchUART8250::InitEarly()
#warning INTITIALIZE UART!!!!!
#endif
}
+
+
void
ArchUART8250::Out8(int reg, uint8 value)
{
@@ -75,4 +78,3 @@ DebugUART8250 *arch_get_uart_8250(addr_t base, int64 clock)
ArchUART8250 *uart = new(buffer) ArchUART8250(base, clock);
return uart;
}
-
diff --git a/src/system/kernel/arch/arm/arch_uart_pl011.cpp
b/src/system/kernel/arch/arm/arch_uart_pl011.cpp
index ea2bc66..0794324 100644
--- a/src/system/kernel/arch/arm/arch_uart_pl011.cpp
+++ b/src/system/kernel/arch/arm/arch_uart_pl011.cpp
@@ -210,8 +210,6 @@ ArchUARTPL011::Barrier()
}
-
-
void
ArchUARTPL011::InitPort(uint32 baud)
{
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