#12221: Refresh rate -setting has no effect. radeon_hd card.
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Reporter: anttiv | Owner: kallisti5
Type: bug | Status: new
Priority: normal | Milestone: R1
Component: Drivers/Graphics/radeon_hd | Version: R1/Development
Resolution: | Keywords:
Blocked By: | Blocking:
Has a Patch: 0 | Platform: x86-64
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Comment (by kallisti5):
oddly, everything looks "ok" from the syslogs:
{{{
================================
1920x1080
2938 KERN: radeon_hd: radeon_set_display_mode: pll 1 selected for
connector 1
2939 KERN: radeon_hd: pll_setup_flags: CRTC: 0, PLL: 1
2940 KERN: radeon_hd: pll_adjust: table 1.2
2941 KERN: radeon_hd: pll_adjust: was: 172798, now: 172790
2942 KERN: radeon_hd: pll_compute_post_divider: vco = 600000
2943 KERN: radeon_hd: pll_compute_post_divider: postDiv = 3
2944 KERN: radeon_hd: pll_compute: using minimum reference divider
2945 KERN: radeon_hd: pll_compute: performing fractional feedback
calculations
2946 KERN: radeon_hd: pll_compute: Calculated pixel clock of 172800
based on:
2947 KERN: radeon_hd: pll_compute: referenceFrequency: 27000;
referenceDivider: 5
2948 KERN: radeon_hd: pll_compute: feedbackDivider: 96;
feedbackDividerFrac: 0
2949 KERN: radeon_hd: pll_compute: postDivider: 3
2950 KERN: radeon_hd: pll_compute: pixel clock 172790 was changed to
172800
2951 KERN: radeon_hd: pll_set: table 1.3
2952 KERN: radeon_hd: pll_set: set adjusted pixel clock 172800 (was
172798)
2953 KERN: radeon_hd: display_crtc_ss
2954 KERN: radeon_hd: display_crtc_set_dtd called to do 1920x1080
2955 KERN: radeon_hd: display_crtc_fb_set: Framebuffer at: 0x0
2956 KERN: radeon_hd: display_crtc_fb_set: Set SurfaceAddress High: 0x0
2957 KERN: radeon_hd: display_crtc_fb_set: Set SurfaceAddress: 0x0
2958 KERN: radeon_hd: display_crtc_fb_set: fb: 1920x1080 (32 bpp)
2959 KERN: radeon_hd: display_crtc_fb_set: fb pitch: 1920
2960 KERN: radeon_hd: display_avivo_crtc_load_lut: crtcID 0
3001 KERN: radeon_hd: D1CRTC_STATUS Value: 0x20002
3002 KERN: radeon_hd: D2CRTC_STATUS Value: 0x10009
3003 KERN: radeon_hd: D1CRTC_CONTROL Value: 0x410311
3004 KERN: radeon_hd: D2CRTC_CONTROL Value: 0x400310
3005 KERN: radeon_hd: D1GRPH_ENABLE Value: 0x1
3006 KERN: radeon_hd: D2GRPH_ENABLE Value: 0x1
3007 KERN: radeon_hd: D1SCL_ENABLE Value: 0x0
3008 KERN: radeon_hd: D2SCL_ENABLE Value: 0x0
3009 KERN: radeon_hd: D1CRTC_BLANK_CONTROL Value: 0x0
3010 KERN: radeon_hd: D2CRTC_BLANK_CONTROL Value: 0x0
================================
1360x768
3033 KERN: radeon_hd: radeon_set_display_mode: pll 1 selected for
connector 1
3034 KERN: radeon_hd: pll_setup_flags: CRTC: 0, PLL: 1
3035 KERN: radeon_hd: pll_adjust: table 1.2
3036 KERN: radeon_hd: pll_adjust: was: 85478, now: 85470
3037 KERN: radeon_hd: pll_compute_post_divider: vco = 600000
3038 KERN: radeon_hd: pll_compute_post_divider: postDiv = 7
3039 KERN: radeon_hd: pll_compute: using minimum reference divider
3040 KERN: radeon_hd: pll_compute: performing fractional feedback
calculations
3041 KERN: radeon_hd: pll_compute: Calculated pixel clock of 85628
based on:
3042 KERN: radeon_hd: pll_compute: referenceFrequency: 27000;
referenceDivider: 5
3043 KERN: radeon_hd: pll_compute: feedbackDivider: 111;
feedbackDividerFrac: 0
3044 KERN: radeon_hd: pll_compute: postDivider: 7
3045 KERN: radeon_hd: pll_compute: pixel clock 85470 was changed to
85628
3046 KERN: radeon_hd: pll_set: table 1.3
3047 KERN: radeon_hd: pll_set: set adjusted pixel clock 85628 (was
85478)
3048 KERN: radeon_hd: display_crtc_ss
3049 KERN: radeon_hd: display_crtc_set_dtd called to do 1360x768
3050 KERN: radeon_hd: display_crtc_fb_set: Framebuffer at: 0x0
3051 KERN: radeon_hd: display_crtc_fb_set: Set SurfaceAddress High: 0x0
3052 KERN: radeon_hd: display_crtc_fb_set: Set SurfaceAddress: 0x0
3053 KERN: radeon_hd: display_crtc_fb_set: fb: 1360x768 (32 bpp)
3054 KERN: radeon_hd: display_crtc_fb_set: fb pitch: 1408
3055 KERN: radeon_hd: display_avivo_crtc_load_lut: crtcID 0
3096 KERN: radeon_hd: D1CRTC_STATUS Value: 0x20002
3097 KERN: radeon_hd: D2CRTC_STATUS Value: 0x10009
3098 KERN: radeon_hd: D1CRTC_CONTROL Value: 0x410311
3099 KERN: radeon_hd: D2CRTC_CONTROL Value: 0x400310
3100 KERN: radeon_hd: D1GRPH_ENABLE Value: 0x1
3101 KERN: radeon_hd: D2GRPH_ENABLE Value: 0x1
3102 KERN: radeon_hd: D1SCL_ENABLE Value: 0x0
3103 KERN: radeon_hd: D2SCL_ENABLE Value: 0x0
3104 KERN: radeon_hd: D1CRTC_BLANK_CONTROL Value: 0x0
3105 KERN: radeon_hd: D2CRTC_BLANK_CONTROL Value: 0x0
}}}
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Ticket URL: <https://dev.haiku-os.org/ticket/12221#comment:4>
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