[SI-LIST] Re: the most desirable power plane design scheme
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: jemanakk@xxxxxxxxxxxxxxxxxxx
- Date: Wed, 31 Mar 2010 09:26:24 -0400
Hi Joseph,
As always, the answer depends on several additional factors.
In your case it may depend on:
- what are (if any) restrictions you have on the board? (shape, size,
thickness, component placement)
- what is the total current if you combine rails (painfully high or
still reasonable)
Within a large range of parameter sets you should be able to make it
either way, and the answer would depend on these additional factors.
Regards,
Istvan Novak
Oracle-Sun
jemanakk@xxxxxxxxxxxxxxxxxxx wrote:
> Hi,
> Thanks for all excellent feedbacks for the coupling cap and power plane
> design.
>
>
> I have another question related to one of my present design:
>
> A board design with 2 FPGA, 5 processors, 3 set of DDR2 DRAM, Gbit
> Ethernets, USB2.0HS, etc.
> There are many voltages common for Processors, FPGAs, PHYs, etc.
>
> What should be the most desirable power plane design scheme?
>
> 1. Dedicated (power islands, isolated by ferrite beads from the common
> power grid/plane) power for each processor, DDR2s, FPGAs etc?
>
> 2. Common power plane for devices with similar voltage (for example: one
> core-voltage-power plane for all processors)?
>
> 3. How much ground-loops and switching noise needs to be considered/worry
> in a multi processor/FPGA/PHYs/DDR2s/etc design on a single board? Is
> there any simplified (rule-of-thumb) board level analysis?
> (Note: I always use HyperLynx based SI analysis for board design, for all
> critical signal routing).
>
> Best regards,
> Joseph
>
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