[SI-LIST] the effect of power noise on IC
- From: Zhangkun <zhang_kun@xxxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Tue, 11 Nov 2003 10:25:36 +0800
Dear all:
In usual document about IC, there is always some constraint about power noise.
For example, the power ground noise should not exceed 5%. We want to analyze
the detailed effects of power noise. Have anybody done simular work? Could you
give some advice?
Best Regards
Zhangkun
2003.11.11
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