[SI-LIST] signal layer between pwr/gnd layers

All,
In trying to remove two layers from a 16 layer PCB I came up with a question
I don't know how to answer short of building a board, which there is not
time for.

I have closed the loop on simulation/modeling vs measurement for a PDS with
embedded capacitor using a 4 mil dielectric and capacitor array.  I want to
say thank you to Sun and Xilinx for the excellent work and papers they have
published in the public domain on the subject.

Now, I am having trouble working out what would happen if I insert a signal
layer in between the planes.  I need three signal layers to be referenced to
a pwr/gnd pair, and that currently takes six layers(G-S-S-P-G-S).  If I can
insert a signal routing layer between pwr and gnd, it drops to five
layers(S-P-S-G-S). This happens on two different pwr rails.  My first
reaction is the only difference would be the ~doubling of the distance
between the planes.  I can decrease this effect by using 3 mil cores.  

After thinking a while longer, it seems like there would be other
differences from the copper in between the planes.  It seems like I should
be able to minimize the effect by using special spacing rules in the signal
layer between the planes to maximize the ratio of dieletric area to copper.
I think this would make the discontinuities in the dielctric(the copper
traces) insignificant.

I have not found a discussion of this specific PDS topic in the archives,
and I apologize in advance if I am repeating something that has already been
discussed.

Any input or thoughts are appreciated, thank you for your time.

Tegan Campbell
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