[SI-LIST] regarding Tprop definition in PCI

  • From: adeel.ahmad@xxxxxx
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 12 May 2003 13:47:52 +0530

hello all,

i have a confusion regarding the Tprop definition given in the PCI
SpecsRev2.2(applicable to PCIX) and explanations given at other places in
books etc.
While some books simply state that Tprop is the total time to travel down
a trace and travel back down the trace.
The PCI Specs says(i quote)-
"For a given driver location, the worst case that must be considered when
determining the value of Tprop is when the signal settles at all other
devices on the bus. The value of Tprop is not affected by the time the
signal settles at the driver output, since devices are not permitted to
drive and receive a signal at the same time."

Following are the questions(consider PCIX system at 133MHz)-
1. Consider the case -
TX -----------------------RX       
in such a case the trace length will have a max. ONE SIDE delay of
2ns(PCIX) since RX(receiver) is placed only at the other end. Am i right
in this?
Now consider another case-
TX -----------------------RX
      |
      RX
in such a case the trace length can be a such that ROUND TRIP delay is  
about 2ns(PCIX) since one RX(receiver) is placed very close to the
TX(Transmitter) end. Am i right in this?
According the the book definition,however, in both cases trace length
must have a ROUND TRIP delay of 2ns irrespective of receiver placement.
Has the book definition taken for granted that receivers are also placed
close to transmitter?

2. What is the significance of specifying Tprop(min) for Conv PCI33 as
0ns while specifying Tprop(min)=0.3ns for PCIX ?

Any enlightment will be welcome.

regards
ADEEL AHMAD
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