[SI-LIST] Re: how to reduce hspice run-time?
- From: "Michael J. Degerstrom" <degers@xxxxxxxxxxxxxxxxxxxx>
- To: yonitz@xxxxxxxxxxxxx, "Si-List (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 9 Oct 2002 07:18:51 -0500
Yoni,
A few suggestions:
1) With HSPICE I've used the multiplier factor. You can take
12 i/o buffers and reduce to two with the multiplier set to 6 for
each buffer. Then you can run the two 6X I/O by switching in phase and then
out of phase to see the effect of signal distortion. You may also have to
reassign the multiplication factors to 11X and 1X and just switch the 1X
buffer as that may be your fastest case. If you look at the worst case noise
and fastest/slowest paths among the combinations described above then you've
most likely bound the problem, i.e., all other combinations that you didn't
simulate will give you results that fall within your results obtained with
the reduce (combined) I/O model.
2) Your I/O model may be a transistor-level fully extracted model with
hundreds of parasitic capacitors and large transistors broken into many
smaller transistors. You may want to use a much simpler model that behaves
almost the same as the original model but runs much more quickly.
3) Your package model may be too detailed. I've been able to reduce these
models using a few techniques but these approaches are very dependant on your
application.
4) When there are large numbers of parallel paths to simulate I usually look
at the best and worst cases and just simulate a "slice" of the problem. For
example, lets assume the worst case coupling results from the package. Then
I'll look at the I/O (including power/ground) assignment of the package and
look for repeating patterns. Let say, for example, there is a pattern that
repeats in groups of 8 I/O. Then I'll just model the signal I/O and pwr/gnd
pins that drive those 8 I/O. There is little more information that can be
gathered from simulating more. In fact, the larger the problem the less time
there is available to look at various combinations that could be investigated.
Good luck,
Mike
On Wednesday 09 October 2002 04:23 am, Yoni Tzafrir wrote:
> hi,
> we are running 12 i/o buffers, connecting to a sub-file which simulates a
> packge (with capacitors and all), driving another 12 i/o (used as
> receivers) through 12 transmision lines (the receivers connects to a
> package too). the pc runs it for 1 hour. it is pantium 4 1.8GHz, with
> 0.5GB RAM.
> is there a way to reduce the time that the simulation runs? maybe reducing
> timestep? how do i do it?
> it is important since we are planing on running much more than 12 buffers.
> yoni
>
> Yonatan (Yoni) Tzafrir
> phone : (972) - 3 - 7552300 (T/L: 351)
> mobile: (972) - 54 - 459469
> fax: (972) - 3 - 6177130
> e-mail: yonitz@xxxxxxxxxxxxx
>
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