Posts for si-list, 10-2002

Browse: Last Month: 09-2002 Main Archive Page Next Month: 11-2002

» [SI-LIST] Re: FET Probe -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: FET Probe -
» [SI-LIST] Xilinx Virtex2 driver spice models -
» [SI-LIST] Re: FET Probe -
» [SI-LIST] FET Probe -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: Routing a 125MHz bus with 1 Bidir, 2 Rcvrs and an input vector -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: spice math question -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: spice math question -
» [SI-LIST] Re: spice math question -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: How to connect to GND planes -
» [SI-LIST] Re: spice math question -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: spice math question -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] spice math question -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] spatial resolution and effective rise time of VNA with TDR time-domainoption -
» [SI-LIST] ESD shielding of the board -
» [SI-LIST] Re: IBIS model generation from Datasheet? How? -
» [SI-LIST] IBIS model generation from Datasheet? How? -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Agilent HPFC5200D or Tachyon XLII -
» [SI-LIST] Re: New Buried Capacitance Material -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: How to connect to GND planes -
» [SI-LIST] Re: How to connect to GND planes -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: How to connect to GND planes -
» [SI-LIST] Re: Why we need to use "Series resistor" atTransmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: New Buried Capacitance Material -
» [SI-LIST] Re: About via model! -
» [SI-LIST] Re: help! hold time calculation of source synchronous timing -
» [SI-LIST] Re: help! hold time calculation of source synchronous timing -
» [SI-LIST] help! hold time calculation of source synchronous timing -
» [SI-LIST] Re: About via model! -
» [SI-LIST] Re: New Buried Capacitance Material -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] New Buried Capacitance Material -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] Re: LVPECL to 1.8V HSTL Conversion -
» [SI-LIST] Re: LVPECL to 1.8V HSTL Conversion -
» [SI-LIST] LVPECL to 1.8V HSTL Conversion -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: spice model of tantalum capacitor -
» [SI-LIST] Recall: LVPECL to 1.8V HSTL Conversion -
» [SI-LIST] LVPECL to 1.8V HSTL Conversion -
» [SI-LIST] Re: The maximum length of a bus? -
» [SI-LIST] Re: spice model of tantalum capacitor -
» [SI-LIST] Re: The maximum length of a bus? -
» [SI-LIST] spice model of tantalum capacitor -
» [SI-LIST] The maximum length of a bus? -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Re: ODD Power Splitter -
» [SI-LIST] Re: ODD Power Splitter -
» [SI-LIST] Max curent allowed in solder ball -
» [SI-LIST] ODD Power Splitter -
» [SI-LIST] Re: High-Speed Communications Alliance -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Re: Multi Board Simulation with DIMM Board from Micron Tech -
» [SI-LIST] Re: Determining load line for LVDS IBIS Device -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Determining load line for LVDS IBIS Device -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] how to derive eye diagram -
» [SI-LIST] Re: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Re: input capacitance representation in IBIS -
» [SI-LIST] Antw: SPARTAN IIE Voltage regulator selection -
» [SI-LIST] SPARTAN IIE Voltage regulator selection -
» [SI-LIST] Re: Interfacing Single ended PECL signal to differenti -
» [SI-LIST] About via model! -
» [SI-LIST] Re: [IBIS] IBIS Seminar -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: Actual experience with LVDS to optical serializers with LVPECL inputs -
» [SI-LIST] Re: pwr-gnd loop inductance measurement -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: [IBIS] IBIS Seminar -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: input capacitance representation in IBIS -
» [SI-LIST] Re: input capacitance representation in IBIS -
» [SI-LIST] Re: [IBIS] IBIS Seminar -
» [SI-LIST] Re: [IBIS] IBIS Seminar -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] pwr-gnd loop inductance measurement -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter? -
» [SI-LIST] IBIS Seminar -
» [SI-LIST] Actual experience with LVDS to optical serializers with LVPECL inputs -
» [SI-LIST] Re: Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? -
» [SI-LIST] Reaching 2 Gbps out of a single-ended interface -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Multi-Plane Equivalent Capacitance in BGA Package -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: Why we need to use "Series resistor"atTransmitter ? -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmitter ? -
» [SI-LIST] Re: Interfacing Single ended PECL signal to differenti -
» [SI-LIST] Pads layout to HSPICE postroute -
» [SI-LIST] Re: input capacitance representation in IBIS -
» [SI-LIST] Re: pwr-gnd loop inductance measurment -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] pwr-gnd loop inductance measurment -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] Re: EM simulator software? -
» [SI-LIST] EM simulator software? -
» [SI-LIST] Re: input capacitance representation in IBIS -
» [SI-LIST] MODEL SELECT -- In IBIS and XTK -
» [SI-LIST] Re: W-element -
» [SI-LIST] Re: SMA replacement -
» [SI-LIST] Re: Need a tool to calculate trace inductance. -
» [SI-LIST] Re: Need a tool to calculate trace inductance. -
» [SI-LIST] Re: Need a tool to calculate trace inductance. -
» [SI-LIST] Re: Need a tool to calculate trace inductance. -
» [SI-LIST] Help on Mentor Graphic's ICX Tool -
» [SI-LIST] Re: Pick & Place Machines operation -
» [SI-LIST] Re: Occurrence-specific properties on SCHEMATIC1/V1, ignoring -
» [SI-LIST] Re: AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: Interfacing Single ended PECL signal to differential PECL pair -
» [SI-LIST] Occurrence-specific properties on SCHEMATIC1/V1, ignoring -
» [SI-LIST] [SI-LIST]Same Pin Number connected to more than one net. -
» [SI-LIST] Re: Help:Who has these models? -
» [SI-LIST] Help:Who has these models? -
» [SI-LIST] Re: AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: Differential trace route question -
» [SI-LIST] Re: AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: W-element -
» [SI-LIST] Re: SMA replacement -
» [SI-LIST] Re: W-element -
» [SI-LIST] Re: W-element -
» [SI-LIST] W-element -
» [SI-LIST] Re: SMA replacement -
» [SI-LIST] Re: AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: SMA replacement -
» [SI-LIST] Re: SMA replacement -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] SMA replacement -
» [SI-LIST] AC Coupling and Differential Pair's Termination -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Re: Low inductance chip capacitor(LICC), IDC -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Re: Interfacing Single ended PECL signal to differential PECL pair -
» [SI-LIST] Re: Search for a part -
» [SI-LIST] Re: Low inductance chip capacitor(LICC), IDC -
» [SI-LIST] Re: Differential trace route question -
» [SI-LIST] Re: Differential trace route question -
» [SI-LIST] Re: Differential trace route question -
» [SI-LIST] Interfacing Single ended PECL signal to differential PECL pair -
» [SI-LIST] Re: Differential trace route question -
» [SI-LIST] Re: Low inductance chip capacitor(LICC), IDC -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] Re: Low inductance chip capacitor(LICC), IDC -
» [SI-LIST] Differential trace route question -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lin es? -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Pick & Place Machines operation -
» [SI-LIST] Re: Low inductance chip capacitor(LICC) -
» [SI-LIST] Low inductance chip capacitor(LICC) -
» [SI-LIST] Low inductance chip capacitor(LICC) -
» [SI-LIST] Re: Search for a part -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: How to Verify C_comp -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lin es? -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Senior SI Positions with TI in Austin -
» [SI-LIST] Re: Beyond Rail Operation in IBIS -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Beyond Rail Operation in IBIS -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: Pick & Place Machines operation -
» [SI-LIST] How to Verify C_comp -
» [SI-LIST] Pick & Place Machines operation -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: AW: Question Regarding Some IBIS Parameters -
» [SI-LIST] AW: Question Regarding Some IBIS Parameters -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR -
» [SI-LIST] Search for a part -
» [SI-LIST] Re: Suggestions on the length of lines -
» [SI-LIST] Question Regarding Some IBIS Parameters -
» [SI-LIST] Re: running scripts with CosmoScope & Hspice -
» (no subject) -
» [SI-LIST] Sigrity Extends Offer for Free Training of SI Tools -
» [SI-LIST] JOB OPPORTUNITIES THAT DO NOT EXIST (VAPOR JOBS) -
» [SI-LIST] running scripts with CosmoScope & Hspice -
» [SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals -
» [SI-LIST] Re: New Senior Signal Integrity Positions available in AustinTX. ...and more!! -
» [SI-LIST] Re: Suggestions on the length of lines -
» [SI-LIST] What must be considered for simulation of 5Gbit differential signals on FR-4 PCB? -
» [SI-LIST] Suggestions on the length of lines -
» [SI-LIST] RESUME -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] Reenviar: RESUME -
» [SI-LIST] Reenviar: RESUME -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] CosmoScope -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: HSpice Models in SPECCTRAQuest -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] HSpice Models in SPECCTRAQuest -
» [SI-LIST] Re: Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] New Senior Signal Integrity Positions available in AustinTX.... -
» [SI-LIST] Impedance calculation of asymmetric coupled lines? -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults -
» [SI-LIST] Re: 2D transmission line theory -
» [SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGPcard ? -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card ? -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults -
» [SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: The model of Cat 5 UTP cable -
» [SI-LIST] Re: SPICE on the cheap -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: The model of Cat 5 UTP cable -
» [SI-LIST] Re: AC Coupling Capacitors for LVPECL Signals -
» [SI-LIST] Re: The model of Cat 5 UTP cable -
» [SI-LIST] The model of Cat 5 UTP cable -
» [SI-LIST] AC Coupling Capacitors for LVPECL Signals -
» [SI-LIST] Opportunity query -
» [SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card? -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Why SSTL_2 does not need 1_25V Pull Up in AGP card? -
» [SI-LIST] Recommendation for edge launched SMA connector for 0.093" board. -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Other mailing lists for system-level SI issues? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: 20H Rule theoretically investigated with simulation. -
» [SI-LIST] Re: Other mailing lists for system-level SI issues? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Other mailing lists for system-level SI issues? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: SPICE on the cheap? -
» [SI-LIST] Re: 20H Rule theoretically investigated with simulation. -
» [SI-LIST] Re: Package Parasitics of 168-PIN DIMM Socket -
» [SI-LIST] Re: 20H Rule theoretically investigated with simulation. -
» [SI-LIST] "Line Errors" in Gigabit Ethernet -
» [SI-LIST] 20H Rule theoretically investigated with simulation. -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: Antw: Package Parasitics of 168-PIN DIMM Socket -
» [SI-LIST] Re: 2D transmission line theory -
» [SI-LIST] Re: how to reduce hspice run-time? -
» [SI-LIST] Re: how to reduce hspice run-time? -
» [SI-LIST] Antw: Package Parasitics of 168-PIN DIMM Socket -
» [SI-LIST] 2D transmission line theory -
» [SI-LIST] Package Parasitics of 168-PIN DIMM Socket -
» [SI-LIST] how to reduce hspice run-time? -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] Re: How to measure package impedance or characteristic for a chip? -
» [SI-LIST] Re: Serpentine Traces -
» [SI-LIST] analog / mixed signal simulation -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces -
» [SI-LIST] Hi all -
» [SI-LIST] complex numbers -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Some Querries regarding Xtalk in traces -
» [SI-LIST] test -
» [SI-LIST] Re: How to measure package impedance or characteristic for a chip? -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] AC Waveform question, clarification -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] Re: AC Waveform question -
» [SI-LIST] AC Waveform question -
» [SI-LIST] Interface of Microphone with Codec -
» [SI-LIST] RE How to -
» [SI-LIST] Re: Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Re: How to measure package impedance or characteristic for a chip? -
» [SI-LIST] Re: Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Recall: Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Why 220ohms at driver end in PECL Terminations -
» [SI-LIST] Re: Differential pair impedance -
» [SI-LIST] Class on Gigabit design at PCB East -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces... unexpected results -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results -
» [SI-LIST] Re: Unconnected pins in a connector carrying differential signals -
» [SI-LIST] Re: Creating IBIS models for a fee? -
» [SI-LIST] Re: Creating IBIS models for a fee? -
» [SI-LIST] How to??? -
» [SI-LIST] Re: Creating IBIS models for a fee? -
» [SI-LIST] Re: Unconnected pins in a connector carrying differentialsignals -
» [SI-LIST] Re: Unconnected pins in a connector carrying differential signals -
» [SI-LIST] Creating IBIS models for a fee? -
» [SI-LIST] Unconnected pins in a connector carrying differential signals -
» [SI-LIST] Re: How to measure package impedance or characteristic for a chip? -
» [SI-LIST] Hyper Transport Probe Details -
» [SI-LIST] Re: Eye pattern with HSPICE -
» [SI-LIST] Eye pattern with HSPICE -
» [SI-LIST] test -- please ignore this mail -
» [SI-LIST] PWB coupling to system enclosures -
» [SI-LIST] How to measure package impedance or characteristic for a chip? -
» [SI-LIST] Resume for Design/Applications Engineer -
» [SI-LIST] FW: Innoveda User's Groups -
» [SI-LIST] dc blocking caps in 10G lines -
» [SI-LIST] Receiver/transmitter offset-sensitivity -
» [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: Hyper Transport Probe -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpectedresults -
» [SI-LIST] Hyper Transport Probe -
» [SI-LIST] RMCEMC October Meeting -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpec... -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... une... -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces ... unexpected results -
» [SI-LIST] Re: Differential microstrip with coplanar ground traces... unexpected results -
» [SI-LIST] Re: Jitter Characterization on a Tester? -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] Differential microstrip with coplanar ground traces ... unexpected results -
» [SI-LIST] Jitter Characterization on a Tester? -
» [SI-LIST] Re: Planar DDR and LVTTL I/O -
» [SI-LIST] Re: Planar DDR and LVTTL I/O -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] SI job opportunity: Technical Marketing Engineer -
» [SI-LIST] Re: SI job opportunity: Technical Marketing Engineer -
» [SI-LIST] Re: Planar DDR and LVTTL I/O -
» [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: 2.5Gbit connectors and cables -
» [SI-LIST] BC Fabricator in Hong Kong -
» [SI-LIST] Re: A SPICE TO IBIS CONVERSION PROBLEM -
» [SI-LIST] Re: 2.5Gbit connectors and cables -