[SI-LIST] Re: controlled impedance requirements
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: kobik@xxxxxxxxxxx
- Date: Mon, 17 Jan 2005 10:46:43 -0500
Kobi,
On outer layers, where copper plating and solder mask increase the
impedance uncertainty,
without premium, +-15% may be easy. On inner layer this figure is
+-10%. Tighter
tolerance is always possible, but you may need to pay more.
If trace impedance is important for you, you may want to select a
trusted PCB fabriactor, give
them an approximate first-cut stackup, and ask the fabricator to
maintain the impedance you
specify. If you have to deal with a lesser-known fabricator, you may
need to do more
home work and have to specify the stackup more directly, by using field
solver simulations.
To come up with a stackup that people can manufacture, you will need to
know the
electrical and mechanical properties of prepregs and cores that is
likely available to the fabricator.
Leaving the task to the fabricator is less work for you, but it has to
be kept in mind that
the fabricator may need to adjust some parameters to meet your target:
they may change
trace width or the dielectric height(s), which in turn may
increase/decrease crosstalk and losses.
Best regards,.
Istvan Novak
SUN Microsystems
kobik74 wrote:
>Hi gurus
>
>How do you specify to the PCB manufacturer the controlled impedance
>requirements
>
>Except the layer stack up, layer thickness (oz), board thickness and
>text that define the controlled impedance for signals in each layer
>do you also define the PCB material type (Er, Silkscreen, Solder
>=85), inner dielectric thickness or you trust the manufacturer to
>reach the controlled impedance?
>
>How much tolerance do you permit?
>
>Thanks in advance
>Kobi
>
>
>
>
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