It could just be the fact that you are not probing at the die pad inside the
BGA, in which case the width of the non-monotonic region that you are measuring
would be approximately equal to twice the BGA package delay.
Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of john h
Sent: Thursday, June 16, 2016 11:35 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] clock signal non-monotonic nature
Hi SI Gurus,
I am new to hardware and I am thankful for your inputs on this .
I am probing a clock signal on the board. The clock is 125MHz differential and
I am probing it at the receiver end. The receiver is of BGA package and I am
probing at the BGA end (via )at the bottom side of the board. ( IC is placed
on the Top side)
The clock pins at the receiver are terminated with 100E internally.
The clock waveform is seen to be of non-monotonic nature. A dip is seen on the
rising and falling edge approximately at 80% of signal level. At that point
during ramp , the signal dips down a bit and then rise again to 100% of the
signal level.
I could not exactly understand on the issue.
To debug further, I removed the AC caps at the receiver (thereby isolating the
receiver) and placed a parallel 100E .And I probed across the 100E.
the signal looks to be completely fine. monotonic and no dips are seen on the
edge.
I could not exactly understand on this. Is the dip seen on the first case is
due to the reflection from the receiver. but the receiver is internally
terminated as per the datasheet. Appreciate your inputs on this.
Thank you,
Johnson
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