[SI-LIST] Re: anti-resonance point when use Embedded Capacitance Material
- From: Cristian Gozzi <cristian.gozzi@xxxxxxxxx>
- To: ken@xxxxxxxxxxxxxxxx
- Date: Fri, 10 May 2013 13:39:34 +0200
Hi Ken
As a good starting point I suggest to try this free Excel tool from ALTERA
http://www.altera.com/technology/signal/power-distribution-network/sgl-pdn.html
comparing to other Excel similar tools, this one has the advantage to
introduce also some layout effect like:
- Embedded capacitance of power planes
- stackup info
- inductance effect of VIAs for BGA
- mounting inductance effect of MLCC capacitors according to its mounting
- X2Y capacitor library
- etc.
last year I did a trial and compared to a complete analysis with Ansys
SIwave and the Impedance was not so far away from what I got with this
Excel tool
But, of course, I spent a little bit more time at beginning to well
tune it and be able to properly introduce the layout effect
Of course from accuracy point of view it´s always better to make a
final verification with Ansys SIwave or Cadence/Sigrity PowerSI or
similar related software
enjoy
Regards
Cristian Gozzi, M.Sc
Infineon Technologies Austria AG
Chip-Package-Board Codesign
2013/5/9 Ken Wyatt <ken@xxxxxxxxxxxxxxxx>:
> Thanks Chas,
> I remember those days...things have progressed greatly.
>
> Do you, or the group, know of affordable simulation S/W (Ansoft, maybe?) that
> would simulate plane resonances? My limited budget won't support multi-G$
> S/W, unfortunately. That would be pretty cool to be able to simulate that. I
> saw a recent demo of HyperLynx that was impressive.
>
> I know Istvan has several Excel calculators that will model PDN impedances.
>
> You coming to the Denver symposium this year?
>
> Cheers, Ken
> ___________________
> Kenneth Wyatt
> Wyatt Technical Services LLC
> Woodland Park, CO
> ken@xxxxxxxxxxxxxxxx
> Web Newsletter
> Connect with me on LinkedIn!
>
> On May 9, 2013, at 2:22 PM, Grasso, Charles wrote:
>
>> Hello Ken,
>>
>> When faced with large areas of pwb that have little or no components, it
>> used common practice for EMI guys to add lossy caps (the lossier the better)
>> to the planes in a regular pattern to minimize the effects of plane
>> resonance. With modern simulation tools, the resonant modes of the planes
>> can be simulated and caps added (in just the right spot!) to reduce the
>> effect.
>>
>> Chas
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>> Behalf Of Istvan Novak
>> Sent: Thursday, May 09, 2013 7:23 AM
>> To: Ken Wyatt
>> Cc: bruce@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: anti-resonance point when use Embedded Capacitance
>> Material
>>
>> Ken,
>> Bypass capacitors with more lossy dielectrics do help somewhat, but the
>> dielectric loss shows up strongly in the ESR only at frequencies much lower
>> than the series resonance frequency, where we usually dont need the higher
>> ESR. Very lossy (and sloppy) dielectrics, such as Z5U and Y5V are good for
>> cheap consumer electronics, but for professional circuits there are many
>> drawbacks and it is not the best thing to use them. Ceramic capacitors with
>> user-defined ESR are available from two of the major capacitor vendors, so
>> they can be used when we need the highest performance and can afford the
>> higher cost for these parts.
>>
>> Regards,
>>
>> Istvan Novak
>> Oracle
>>
>>
>>
>>
>> On 5/9/2013 9:00 AM, Ken Wyatt wrote:
>>> Hi Group & Bruce,
>>>
>>> I'm kind of a "newby" when it comes to SI, but am reading Lee Richey's
>>> books on the subject.
>>>
>>> One thing he recommends for PDN designs is the use of bypass
>>> capacitors with a more lossy dielectric (higher ESR), such as X5R, Z5U
>>> or Y5V, to dampen the anti-resonance. Would this be a reasonable thing
>>> to try?
>>>
>>> Ken
>>> ___________________
>>> Kenneth Wyatt
>>> Wyatt Technical Services LLC
>>> Woodland Park, CO
>>> ken@xxxxxxxxxxxxxxxx <mailto:ken@xxxxxxxxxxxxxxxx> Web
>>> <http://www.emc-seminars.com> Newsletter
>>> <http://emc-seminars.us1.list-manage.com/subscribe?u˜7f203d1f64dd89f
>>> 06b0c3f5&id 0f29a904> Connect with me on LinkedIn
>>> <http://www.linkedin.com/in/kennethwyatt>!
>>>
>>> On May 9, 2013, at 5:16 AM, Istvan Novak wrote:
>>>
>>>> Hi Bruce,
>>>>
>>>> The anti-resonance between the static capacitance of planes and
>>>> inductance of bypass capacitors will always be present unless you
>>>> either match the plane impedance with the ESRs of capacitors or
>>>> overwhelm the antiresonance with MANY low-inductance bypass
>>>> capacitors. The antiresonance is present with any laminate material, thin
>>>> or thick.
>>>> When you use thin laminates (Embedded Capacitance Material), the
>>>> resonance magnitude and frequency both get lower with respect to a
>>>> thicker laminate. First you have to determine whether the resonance
>>>> causes a problem for power, signal integrity and EMI. If you dont
>>>> excite the resonance, you dont need to care.
>>>>
>>>> Regards,
>>>>
>>>> Istvan Novak
>>>> Oracle
>>>>
>>>>
>>>>
>>>>
>>>> On 5/9/2013 2:26 AM, Bruce wrote:
>>>>> Hi Expert
>>>>>
>>>>>
>>>>> We use Embedded Capacitance Material for better PDN and less
>>>>> capacitor component. According to PDN Simulation. We notice that is
>>>>> an anti-resonance point between capacitor and Plane.
>>>>>
>>>>>
>>>>>
>>>>> We can find that when use Embedded Capacitance Material. There are
>>>>> much better in most frequency but near anti-resonance point.
>>>>>
>>>>>
>>>>>
>>>>> In this case. We have to solution.
>>>>>
>>>>> 1. Try to reduce the anti-resonance point. We need many high
>>>>> frequency
>>>>> capacitor component. That is not good because we want to reduce the
>>>>> number of capacitor component. Our purpose is reduce 70% number of
>>>>> capacitor component.
>>>>>
>>>>> 2. Keep this anti-resonance point. That maybe have a risk if
>>>>> there is
>>>>> some noise by chance in this frequency
>>>>>
>>>>>
>>>>>
>>>>> How about your suggestion? Please let me know if my question is not
>>>>> clear enough.
>>>>>
>>>>> Thanks
>>>>>
>>>>>
>>>>>
>>>>> Best Regards,
>>>>>
>>>>> Bruce Wu
>>>>>
>>>>>
>>>>>
>>>>>
>>>>
>>>>
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