[SI-LIST] X2Y 'zero' inductance caps
- From: S Tatlow <s_tatlow@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 6 Mar 2002 15:34:38 +0000 (GMT)
Hi people,
so, having discovered the idea of 'zero' inductance caps through this great
communication
chain, I thought I would try and 'tap' the chain a little further: my idea for
an application
of this X2Y technology would be as decoupling between 2 core and I/O power
supply planes (20
BGAs/>7000 pins in 230x65mm area, drawing up to 20A), and the ground planes of
the following
stackup:
L1 top sig
L2 gnd
L3 internal sig 1
L4 internal sig 2
L5 I/O power
L6 core power
L7 internal sig 3
L8 internal sig 4
L9 gnd
L10 bottom sig
This stackup seems to me to offer the best solution, but maybe falls down (with
regard to
return current paths) when looking to swap high speed signals from L4 to L7 in
areas where
there are no bypass capacitors for BOTH voltages. Ok, there is some degree of
inter-plane
capacitance, but if I am right, the X2Y caps would seem to be a much better
solution, not to
mention the obvious advantage of halving the number of components.
In fact, any comments on this technology would probably be helpful, as these
seem to be
relatively new/hard to come by, and I _guess_ they are going to be expensive
(probably too
expensive for 'plain old' decoupling?), so justification in specifying would be
necessary (and
obviously, if I have overlooked other downpoints of the above stackup, then
feel free to shoot
me down in flames ;-) ).
Sol
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