[SI-LIST] Trace's width variant designed on PCB!
- From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
- To: "Si-List (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Feb 2003 20:05:44 +0800
Hi All SI Friends:
I am doing an analysis about xxx chipset on motherboard. From this chipset
design guide, it claims high byte signals for DDR memory (they have longer
trace length) should be routed for variant width. I think this has some
thing to do with long trace. Trace's width increased gradually if total
length on PCB over some spec. I know that inductance will affect the SI and
timing dominantly in microstrip structure, so narrower trace will have
higher inductance when trace is long ( I found that there exist ledge on
rising edge when width is narrow). So increase trace width will decrease
inductance under the same length. I found that high and low time of input
signal will become smaller, there leaves less margin for setup and hold
time. So I think this is the reason why it needs variant width designed. But
I wonder that why reflection voltage could be neglected? I estimate that
amplitude of reflection voltage is around 450mV. This quantity is larger
related to DDR signal. I can't proceed a detail calculation further, but why
reflection voltage will not degrade the timing but inductance does in this
case. Can anyone propose any suggestion or comment? Thanks!
Jack
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