Posts for si-list, 02-2003

Browse: Last Month: 01-2003 Main Archive Page Next Month: 03-2003

» [SI-LIST] Re: Coupling THROUGH a plane? -
» [SI-LIST] Re: Coupling THROUGH a plane? -
» [SI-LIST] Coupling THROUGH a plane? -
» [SI-LIST] Hspice diff sim -
» [SI-LIST] Re: HSPICE syntax -
» [SI-LIST] Re: Guidelines required for high speed PCB design -
» [SI-LIST] European IBIS Summit@DATe2003 - Agenda -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Re: Modeling Pre-Emphasis in IBIS -
» [SI-LIST] Modeling Pre-Emphasis in IBIS -
» [SI-LIST] Re: Guidlines required for high speed PCB design -
» [SI-LIST] HSPICE syntax -
» [SI-LIST] Re: Ground nodes in spice -
» [SI-LIST] Re: Ground nodes in spice -
» [SI-LIST] Re: compact-PCI design for test question -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Announcement for the FDIP'03 Workshop -
» [SI-LIST] Re: Ground nodes in spice -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - March 25 meeting -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Re: Ground nodes in spice -
» [SI-LIST] Re: Ground nodes in spice -
» [SI-LIST] 8b/10b program using MATLAB -
» [SI-LIST] Ground nodes in spice -
» [SI-LIST] compact-PCI design for test question -
» [SI-LIST] SPI 2003 submission deadline -
» [SI-LIST] Re: Guidlines required for high speed PCB design -
» [SI-LIST] Re: IBIS & Cable -
» [SI-LIST] Transmitter Chip. -
» [SI-LIST] Ferrite filter -
» [SI-LIST] Forked/Sectioned IBIS Package models -
» [SI-LIST] Re: IBIS & Cable -
» [SI-LIST] Re: IBIS & Cable -
» [SI-LIST] Re: IBIS & Cable -
» [SI-LIST] Guidlines required for high speed PCB design -
» [SI-LIST] IBIS & Cable -
» [SI-LIST] Re: Maximum Bandwidth in ISM band -
» [SI-LIST] Re: Couplin capacitance -
» [SI-LIST] Design of op-amp -
» [SI-LIST] Maximum Bandwidth in ISM band -
» [SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] More lossy t-line questions - attenuation per unit length and ln functions -
» [SI-LIST] AW: si-list Digest V3 #56 -
» [SI-LIST] Re: Termination of un-used clocks -
» [SI-LIST] Re: Termination of un-used clocks -
» [SI-LIST] Re: Software AppCAD -
» [SI-LIST] WARNING: [NET0099] -
» [SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines -
» [SI-LIST] how to simulate with S parameters -
» [SI-LIST] Re: Software AppCAD -
» [SI-LIST] Re: Software AppCAD -
» [SI-LIST] Software AppCAD -
» [SI-LIST] Re: Couplin capacitance -
» [SI-LIST] Re: Termination of un-used clocks -
» [SI-LIST] [ÀüÃ¼È¸½Å] Impedance matching with CPW -
» [SI-LIST] Re: Termination of un-used clocks -
» [SI-LIST] Termination of un-used clocks -
» [SI-LIST] Re: Solder migration during RFIC testing -
» [SI-LIST] question about IBIS's V-T curve Scaleing ? -
» [SI-LIST] Re: Shield ground isolation -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines -
» [SI-LIST] Re: Shield ground isolation - logic/chassis ground connection -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Logic Family with ensured low outputs when no poweris there -
» [SI-LIST] Re: Impedance matching with CPW -
» [SI-LIST] Re: Shield ground isolation -
» [SI-LIST] Re: De-emphasis in 3GIO -
» [SI-LIST] Re: Shield ground isolation -
» [SI-LIST] IBIS Models -
» [SI-LIST] Impedance matching with CPW -
» [SI-LIST] Re: Solder migration during RFIC testing -
» [SI-LIST] Re: Shield ground isolation -
» [SI-LIST] Solder migration during RFIC testing -
» [SI-LIST] ��: CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions -
» [SI-LIST] Re: Shield ground isolation -
» [SI-LIST] Shield ground isolation -
» [SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? -
» [SI-LIST] Re: Couplin capacitance -
» [SI-LIST] Shield ground isolation -
» [SI-LIST] Signal integrity positions at NVIDIA (Santa Clara, Ca) -
» [SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? -
» [SI-LIST] Re: Logic Family with ensured low outputs when no power isthere -
» [SI-LIST] Re: PCI 33Mhz cables. -
» [SI-LIST] Re: De-emphasis in 3GIO -
» [SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? -
» [SI-LIST] Re: De-emphasis in 3GIO -
» [SI-LIST] PDS Capacitor Mounting Details for Lowest Inductance? -
» [SI-LIST] Re: De-emphasis in 3GIO -
» [SI-LIST] Re: De-emphasis in 3GIO -
» [SI-LIST] Re: DECOUPLING DOUBT -
» [SI-LIST] DECOUPLING DOUBT -
» [SI-LIST] Logic Family with ensured low outputs when no power is there -
» [SI-LIST] European IBIS Summit@DATe2003 - Agenda + 3rd call for participation and presentations -
» [SI-LIST] CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions -
» [SI-LIST] Trace's width variant designed on PCB! -
» [SI-LIST] signal integrity step by step -
» [SI-LIST] Re: SI & EMC certifications -
» [SI-LIST] SI & EMC certifications -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] FW: Antw: Hyperlynx -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Trace Dimensions ?? -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Trace Dimensions ?? -
» [SI-LIST] Re: Antw: Trace Dimensions ?? -
» [SI-LIST] hspice connecting to an ibis component -
» [SI-LIST] Re: Compliant pad on pcb -
» [SI-LIST] Antw: Hyperlynx -
» [SI-LIST] Re: Trace Dimensions ?? -
» [SI-LIST] Re: Differential TDR in HSPICE -
» [SI-LIST] About uneven loads -
» [SI-LIST] Re: Trace length vs Delay; Trace length vs Rise/Fallti me -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Antw: Trace Dimensions ?? -
» [SI-LIST] Trace Dimensions ?? -
» [SI-LIST] Re: On die SI discussion forum -
» [SI-LIST] Compliant pad on pcb -
» [SI-LIST] On die SI discussion forum -
» [SI-LIST] Re: Regarding "unbonded region" in PCB stackup -
» [SI-LIST] FW: RE02 cabling problem -
» [SI-LIST] Re: off-diagonal resistance and conductanceelements -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: Regarding "unbonded region" in PCB stackup -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Differential TDR in HSPICE -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: Low-Temp Twisted pair cable -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: property about symmetrical network -
» [SI-LIST] Re: Split planes and ground return wires -
» [SI-LIST] Split planes and ground return wires -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Couplin capacitance -
» [SI-LIST] Low-Temp Twisted pair cable -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductanceelements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Reducing slew rate -
» [SI-LIST] Re: HFSS Issue Zpi Zpv (continued..) -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] Re: off-diagonal resistance and conductance elements -
» [SI-LIST] off-diagonal resistance and conductance elements -
» [SI-LIST] Re: Trace length vs Delay; Trace length vs Rise/Fallti me -
» [SI-LIST] Re: mux/demux for GIGA Ethernet diff. lines -
» [SI-LIST] Trace length vs Delay; Trace length vs Rise/Fall time -
» [SI-LIST] Hspice and Skin Effect -
» [SI-LIST] Re: digital vector -
» [SI-LIST] Re: digital vector -
» [SI-LIST] De-emphasis in 3GIO -
» [SI-LIST] Re: SERDES with pre-emphasis -
» [SI-LIST] [Fwd: RE: Re: dielectric loss question] -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] mux/demux for GIGA Ethernet diff. lines -
» [SI-LIST] Re: digital vector -
» [SI-LIST] New low inductance second level Interconnection (module to card) (SpringLand Grid Array) -
» [SI-LIST] SERDES with pre-emphasis -
» [SI-LIST] FW: Resistor in Board -
» [SI-LIST] Resistor in Board -
» [SI-LIST] digital vector -
» [SI-LIST] Regarding "unbonded region" in PCB stackup -
» [SI-LIST] RMCEMC Slide correction -
» [SI-LIST] Re: Using of Distributed Package model for simulation -
» [SI-LIST] RMCEMC January Presentation Download available -
» [SI-LIST] Re: PECL termination technique? -
» [SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] HFSS Issue Zpi Zpv (continued..) -
» [SI-LIST] radiated emi data -
» [SI-LIST] Re: PECL termination technique? -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: PECL termination technique? -
» [SI-LIST] Re: PECL termination - won't work ? -
» [SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up -
» [SI-LIST] Controlled Impedance Calculation for a 8-Layer Stack-up -
» [SI-LIST] Using of Distributed Package model for simulation -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] property about symmetrical network -
» [SI-LIST] Re: Total impedance of trace, plated holes and connectors -
» [SI-LIST] Total impedance of trace, plated holes and connectors -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: Harvy Wilbur dielectric loss question -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Experienced SI/EMC Engineer Available -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Re: Even and odd impedances -
» [SI-LIST] Even and odd impedances -
» [SI-LIST] Re: S-parameter for differential signals in Hspice -
» [SI-LIST] Re: PECL termination technique? -
» [SI-LIST] Re: PECL termination technique? -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] PECL termination - won't work ? -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] PECL termination technique? -
» [SI-LIST] Re: S-parameter for differential signals in Hspice -
» [SI-LIST] Re: S-parameter for differential signals in Hspice -
» [SI-LIST] Re: S-parameter for differential signals in Hspice -
» [SI-LIST] S-parameter for differential signals in Hspice -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Re: Mixed Mode S-Parameters for more than one diff pair. -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: LINPAR -
» [SI-LIST] Re: Audio And Fan Circuits interference -
» [SI-LIST] Re: IBIS I/O model in HSPICE question -
» [SI-LIST] Mixed Mode S-Parameters for more than one diff pair. -
» [SI-LIST] Re: I disagree, I liked your SI list posting -
» [SI-LIST] Re: IBIS I/O model in HSPICE question -
» [SI-LIST] Audio And Fan Circuits interference -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi differe nce -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: CPW in HFSS, ask for help -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: IBIS I/O model in HSPICE question -
» [SI-LIST] Re: IBIS I/O model in HSPICE question -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: tools questions on the reflector -
» [SI-LIST] Re: IBIS I/O model in HSPICE question -
» [SI-LIST] IBIS I/O model in HSPICE question -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: CPW in HFSS, ask for help -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: Wafer probing on Al pads -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Question related to HFSS: Zpi, Zpv, Zvi difference -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Re: dielectric loss question -
» [SI-LIST] Re: Traces referenced to gnd/power planes in package -
» [SI-LIST] Re: Wafer probing on Al pads -
» [SI-LIST] Re: Wafer probing on Al pads -
» [SI-LIST] Re: a bug in hspice -
» [SI-LIST] Re: Help... -
» [SI-LIST] dielectric loss question -
» [SI-LIST] Re: a bug in hspice -
» [SI-LIST] Re: about n-well parameters in standard 0.18um logic cmosprocess -
» [SI-LIST] Re: Converting Orcad to Ansoft -
» [SI-LIST] Re: Converting Orcad to Ansoft -
» [SI-LIST] Wafer probing on Al pads -
» [SI-LIST] Re: Converting Orcad to Ansoft -
» [SI-LIST] Converting Orcad to Ansoft -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: CPW in HFSS, ask for help -
» [SI-LIST] Re: Need HFSS CPW Solution Example !!help -
» [SI-LIST] Re: Traces referenced to gnd/power planes in package -
» [SI-LIST] TDR Training and Signal Integrity Papers -
» [SI-LIST] Re: Traces referenced to gnd/power planes in package -
» [SI-LIST] LINPAR -
» [SI-LIST] Re: Help... -
» [SI-LIST] Re: Need HFSS CPW Solution Example !!help -
» [SI-LIST] Re: Need HFSS CPW Solution Example !!help -
» [SI-LIST] Need HFSS CPW Solution Example !!help -
» [SI-LIST] Traces referenced to gnd/power planes in package -
» [SI-LIST] Max operating frequency of LVDS driver -
» [SI-LIST] Re: How accurate is HSPICE's field solver? (#2) -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] about n-well parameters in standard 0.18um logic cmos process -
» [SI-LIST] Re: Help... -
» [SI-LIST] Re: a bug in hspice -
» [SI-LIST] RMCEMC Presentation download -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: Help... -
» [SI-LIST] Re: Help... -
» [SI-LIST] Re: a bug in hspice -
» [SI-LIST] Re: Help... -
» [SI-LIST] a bug in hspice -
» [SI-LIST] Max operating frequency of LVDS driver -
» [SI-LIST] Help... -
» [SI-LIST] testing -
» [SI-LIST] testing -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: RLGC matrices of a differential pair line -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: RLGC matrices of a differential pair line -
» [SI-LIST] RLGC matrices of a differential pair line -
» [SI-LIST] Trace width -
» [SI-LIST] Re: Estimation of trace capacitance -
» [SI-LIST] Re: Where and how the Ground Noise Come from? -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] UPDATED SI Measurement Class: GTL 260 -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Estimation of trace capacitance -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Estimation of trace capacitance -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Estimation of trace capacitance -
» [SI-LIST] Broad based lead engineer available (yes, Signal Integrity too) -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: random vectors -
» [SI-LIST] Re: Current capacity of a Solder Ball -
» [SI-LIST] Re: random vectors -
» [SI-LIST] Current capacity of a Solder Ball -
» [SI-LIST] Re: random vectors -
» [SI-LIST] Re: back plane vs mother board -
» [SI-LIST] Re: random vectors -
» [SI-LIST] Re: random vectors -
» [SI-LIST] random vectors -
» [SI-LIST] back plane vs mother board -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] LED measurements -
» [SI-LIST] European IBIS Summit@DATe2003 - 2nd call for participation and presentations -
» [SI-LIST] Antw: Simulator -
» [SI-LIST] Simulator -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] New Paper: Low Inductance Measurements -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Buffer for 2.5Gb/s data -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] Re: fanout -
» [SI-LIST] fanout -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] Re: UN Petition to Stop War- Spread the Peace -
» [SI-LIST] UN Petition to Stop War- Spread the Peace -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: Help - experience with Ansoft "F"dependentsources???? -
» [SI-LIST] Help - experience with Ansoft "F" dependent sources???? -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] placement of bias resistors on differential traces -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: EMI fixed by flooding? -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: EMI fixed by flooding? -
» [SI-LIST] Re: load of a High-impedant I/O on a bus -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Where and how the Ground Noise Come from? -
» [SI-LIST] Re: load of a High-impedant I/O on a bus -
» [SI-LIST] Re: Where and how the Ground Noise Come from? -
» [SI-LIST] Re: Conductor Ampacity question -
» [SI-LIST] IBIS Development Studio -
» [SI-LIST] Re: Where and how the Ground Noise Come from? -
» [SI-LIST] Re: Where and how the Ground Noise Come from? -
» [SI-LIST] load of a High-impedant I/O on a bus -
» [SI-LIST] Where and how the Ground Noise Come from? -