[SI-LIST] Re: T-line resonant frequency
- From: Istvan Novak <Istvan.Novak@xxxxxxx>
- To: forsilist@xxxxxxxxx
- Date: Tue, 27 Apr 2004 11:51:45 -0400
Raj,
Any reactance along the transmission line will
change the virtual electrical length of the line.
Capacitive load makes the line seemingly longer.
This is what may be the reason. You can verify this
running AC simulations. Change your driver from
pulse to swept-frequency sine wave (may need to replace
your driver model with an independent source) and=20
look for the frequency responses: input impedance=20
seen by the driver and transfer responses from=20
source voltage to load voltage. You probably will
see extrema of these transfer functions lining up
with your worst-case jitter.
Regards,
Istvan=20
raj singh wrote:
>=20
> Steve, sorry for such a 'to the point' question.
> I should have been more descriptive....
> I have a DDR data driver to be used in point-to-point
> source terminated(unterminated) enviorment. I am using
> spice simulation to find out for what T-line delay
> driver gives worst jitter, rest all are fixed (PRBS,
> pkg parasitics, clk freq, Z0=3D50 ...etc). I am
> simulating just one driver.
> I found that it is not Td=3Dlambda,lambda/2,lambda/4
> which gives worst jitter, but values slightly less
> than this. WHY THIS? is what I want to clarify.
>=20
> Thanks
> Rjt
>=20
> --- raj singh <forsilist@xxxxxxxxx> wrote:
> > Hi all,
> >
> > What t-line delay (in terms clock period) will show
> > the worst driver jitter. Some papers, which i have
> > gone through, says it is when Td equals clock
> > period,
> > half the clock period or quarter the clock period
> > (calls it resonant frequency).
> > But cannot able to think of why is it so? Tried to
> > devolope some of my own ideas, but want to discuss
> > with the list to get correct answer.
> >
> > Thanks and regards,
> > Rjt
> >
> >
> >
> >
> >
> >
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>=20
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--=20
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